# HG changeset patch # User punk # Date 1272198707 14400 # Node ID 50af57801d6e696e93157f3891a95b7e95fb7f7e # Parent 295314b1622059b893976d53bc7d50333a92d1c1 [svn r12] working on getting audio pipe processor working diff -r 295314b16220 -r 50af57801d6e modules/bluespec/Pygar/core/Processor.bsv --- a/modules/bluespec/Pygar/core/Processor.bsv Fri Apr 23 09:35:02 2010 -0400 +++ b/modules/bluespec/Pygar/core/Processor.bsv Sun Apr 25 08:31:47 2010 -0400 @@ -30,6 +30,7 @@ import SFIFO::*; import RWire::*; +import Trace::*; import BFIFO::*; import MemTypes::*; import ProcTypes::*; @@ -37,23 +38,24 @@ import BranchPred::*; //import PathTypes::*; This is only there to force the debugging -import Trace::*; - //AWB includes `include "asim/provides/low_level_platform_interface.bsh" `include "asim/provides/soft_connections.bsh" `include "asim/provides/common_services.bsh" // Local includes -`include "asim/provides/processor_library.bsh" +//`include "asim/provides/processor_library.bsh" (included above directly) `include "asim/rrr/remote_server_stub_PROCESSORSYSTEMRRR.bsh" `include "asim/provides/common_services.bsh" `include "asim/dict/STATS_PROCESSOR.bsh" -interface ProcStats; - interface Get#(Stat) num_cycles; - interface Get#(Stat) num_inst; -endinterface +// Local includes. Look for the correspondingly named .awb files +// workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/ +// to find the actual Bluespec files which are used to generate +// these includes. These files are specific to this audio processing +// pipeline + +`include "asim/provides/audio_processor_types.bsh" interface CPUToHost; method Bit#(32) cpuToHost(int req); @@ -68,14 +70,19 @@ // Interface for enabling/disabling statistics on the rest of the core interface Get#(Bool) statsEn_get; - // Interface for collecting statistics. - interface ProcStats stats; - // Interface to host interface CPUToHost tohost; + // Interface to Audio Pipeline + interface Audio audio; + endinterface +//The full interface for this is as below in the common file for audioProcessorTypes.bsv +interface Audio; + interface Put#(AudioProcessorUnit) audioSampleInput; + interface Get#(AudioProcessorUnit) audioSampleOutput; +endinterface typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits); @@ -250,14 +257,19 @@ FIFO#(DataReq) dataReqQ <- mkBFIFO1(); FIFO#(DataResp) dataRespQ <- mkFIFO(); - // Statistics state - Reg#(Stat) num_cycles <- mkReg(0); - Reg#(Stat) num_inst <- mkReg(0); + // Audio I/O + FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO; + FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO; + + + // Statistics state (2010) +// Reg#(Stat) num_cycles <- mkReg(0); +// Reg#(Stat) num_inst <- mkReg(0); //Or: - // Statistics state - //STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT); - //STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT); + // Statistics state + STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT); + STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT); //----------------------------------------------------------- // Rules @@ -515,7 +527,7 @@ pcQ.deq(); if ( cp0_statsEn ) - num_inst <= num_inst+1; + num_inst.incr(); endrule @@ -541,20 +553,25 @@ rule inc_num_cycles; if ( cp0_statsEn ) - num_cycles <= num_cycles+1; + num_cycles.incr(); endrule -// THis rule breaks things -// rule handleCPUToHost; -// let req <- server_stub.acceptRequest_ReadCPUToHost(); -// case (req) -// 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost); -// 1: server_stub.sendResponse_ReadCPUToHost(pc); -// 2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage))); -// endcase -// endrule -//----------------------------------------------------------- -// My Adds -//----------------------------------------------------------- + +(* conservative_implicit_conditions *) + rule handleCPUToHost; + let req <- server_stub.acceptRequest_ReadCPUToHost(); + case (req) + 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost); + 1: server_stub.sendResponse_ReadCPUToHost(pc); + 2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage))); + endcase + endrule + + // for now, we don't do anything. + rule connectAudioReqResp; + $display("FIR copies a data"); + outAudioFifo.enq(inAudioFifo.first); + outAudioFifo.deq; + endrule //----------------------------------------------------------- // Methods @@ -571,11 +588,6 @@ interface Get statsEn_get = toGet(asReg(cp0_statsEn)); - interface ProcStats stats; - interface Get num_cycles = toGet(asReg(num_cycles)); - interface Get num_inst = toGet(asReg(num_inst)); - endinterface - interface CPUToHost tohost; method Bit#(32) cpuToHost(int req); return (case (req) @@ -586,5 +598,11 @@ endmethod endinterface + interface Audio audio; + interface audioSampleInput = fifoToPut(inAudioFifo); + interface audioSampleOutput = fifoToGet(outAudioFifo); + endinterface + + endmodule diff -r 295314b16220 -r 50af57801d6e modules/bluespec/Pygar/core/audio_core.awb --- a/modules/bluespec/Pygar/core/audio_core.awb Fri Apr 23 09:35:02 2010 -0400 +++ b/modules/bluespec/Pygar/core/audio_core.awb Sun Apr 25 08:31:47 2010 -0400 @@ -1,16 +1,16 @@ -%name audio core -%desc Instantiates a soft core used for audio, wrapped in the audio pipeline interface +i%name Simple Audio Processor Core +%desc Instantiates a processor, some caches, and a memory arbiter -%provides audio_pipeline +%provides core -%requires audio_pipeline_types -%requires core -%requires funcp_simulated_memory -%requires funcp_base_types -%requires hasim_common - +%requires mem_arb +%requires instruction_cache +%requires data_cache +%requires processor +%requires processor_library %attributes 6_375 -%public FIRFilterPipeline.bsv +%public audioCore.bsv + diff -r 295314b16220 -r 50af57801d6e modules/bluespec/Pygar/core/core.awb --- a/modules/bluespec/Pygar/core/core.awb Fri Apr 23 09:35:02 2010 -0400 +++ b/modules/bluespec/Pygar/core/core.awb Sun Apr 25 08:31:47 2010 -0400 @@ -9,7 +9,7 @@ %requires processor %requires processor_library -%attributes 6_375 +%attributes PYGAR %public Core.bsv diff -r 295314b16220 -r 50af57801d6e modules/bluespec/Pygar/core/processor.awb --- a/modules/bluespec/Pygar/core/processor.awb Fri Apr 23 09:35:02 2010 -0400 +++ b/modules/bluespec/Pygar/core/processor.awb Sun Apr 25 08:31:47 2010 -0400 @@ -1,5 +1,5 @@ -%name 3-Stage Audio Processor -%desc 3-Stage Processor, one stage per cycle. +%name 3-Stage Audio Processor +%desc 3-Stage Processor, with audio in one stage per cycle. %provides processor diff -r 295314b16220 -r 50af57801d6e modules/bluespec/Pygar/core/processor_library.awb --- a/modules/bluespec/Pygar/core/processor_library.awb Fri Apr 23 09:35:02 2010 -0400 +++ b/modules/bluespec/Pygar/core/processor_library.awb Sun Apr 25 08:31:47 2010 -0400 @@ -3,7 +3,7 @@ %provides processor_library -%attributes 6_375 +%attributes PYGAR %public Trace.bsv BFIFO.bsv MemTypes.bsv BRegFile.bsv BranchPred.bsv diff -r 295314b16220 -r 50af57801d6e modules/bluespec/Pygar/lab4/core.awb --- a/modules/bluespec/Pygar/lab4/core.awb Fri Apr 23 09:35:02 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/core.awb Sun Apr 25 08:31:47 2010 -0400 @@ -9,7 +9,7 @@ %requires processor %requires processor_library -%attributes 6_375 +%attributes PYGAR %public Core.bsv diff -r 295314b16220 -r 50af57801d6e modules/bluespec/Pygar/lab4/data_cache.awb --- a/modules/bluespec/Pygar/lab4/data_cache.awb Fri Apr 23 09:35:02 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/data_cache.awb Sun Apr 25 08:31:47 2010 -0400 @@ -3,7 +3,7 @@ %provides data_cache -%attributes 6_375 +%attributes PYGAR %public DataCacheBlocking.bsv %public DataCache.dic diff -r 295314b16220 -r 50af57801d6e modules/bluespec/Pygar/lab4/instruction_cache.awb --- a/modules/bluespec/Pygar/lab4/instruction_cache.awb Fri Apr 23 09:35:02 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/instruction_cache.awb Sun Apr 25 08:31:47 2010 -0400 @@ -3,7 +3,7 @@ %provides instruction_cache -%attributes 6_375 +%attributes PYGAR %public InstCacheBlocking.bsv %public InstCache.dic diff -r 295314b16220 -r 50af57801d6e modules/bluespec/Pygar/lab4/mem_arb.awb --- a/modules/bluespec/Pygar/lab4/mem_arb.awb Fri Apr 23 09:35:02 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/mem_arb.awb Sun Apr 25 08:31:47 2010 -0400 @@ -3,7 +3,7 @@ %provides mem_arb -%attributes 6_375 +%attributes PYGAR %public MemArb.bsv diff -r 295314b16220 -r 50af57801d6e modules/bluespec/Pygar/lab4/processor.awb --- a/modules/bluespec/Pygar/lab4/processor.awb Fri Apr 23 09:35:02 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/processor.awb Sun Apr 25 08:31:47 2010 -0400 @@ -3,7 +3,7 @@ %provides processor -%attributes 6_375 +%attributes PYGAR %public Processor.bsv ProcTypes.bsv %public Processor.dic diff -r 295314b16220 -r 50af57801d6e modules/bluespec/Pygar/lab4/processor_library.awb --- a/modules/bluespec/Pygar/lab4/processor_library.awb Fri Apr 23 09:35:02 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/processor_library.awb Sun Apr 25 08:31:47 2010 -0400 @@ -3,6 +3,6 @@ %provides processor_library -%attributes 6_375 +%attributes PYGAR -%public Trace.bsv BFIFO.bsv MemTypes.bsv FIFOUtility.bsv GetPutExt.bsv SFIFO.bsv CBUFF.bsv BRegFile.bsv BranchPred.bsv \ No newline at end of file +%public Trace.bsv BFIFO.bsv MemTypes.bsv FIFOUtility.bsv GetPutExt.bsv SFIFO.bsv CBUFF.bsv BRegFile.bsv BranchPred.bsv diff -r 295314b16220 -r 50af57801d6e modules/bluespec/Pygar/lab4/processor_system.awb --- a/modules/bluespec/Pygar/lab4/processor_system.awb Fri Apr 23 09:35:02 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/processor_system.awb Sun Apr 25 08:31:47 2010 -0400 @@ -8,7 +8,7 @@ %requires funcp_base_types %requires hasim_common -%attributes 6_375 +%attributes PYGAR %sources -t BSV -v PUBLIC ProcessorSystem.bsv %sources -t CPP -v PUBLIC ProcessorSystem.cpp