rlm@8: import RegFile::*;
rlm@8: import RWire::*;
rlm@8: import ProcTypes::*;
rlm@8: 
punk@58: `include "asim/provides/low_level_platform_interface.bsh"
punk@58: `include "asim/provides/soft_connections.bsh"
punk@58: `include "asim/provides/fpga_components.bsh"
punk@58: `include "asim/provides/common_services.bsh"
punk@58: 
rlm@8: //-----------------------------------------------------------
rlm@8: // Register file module
rlm@8: //-----------------------------------------------------------
rlm@8: 
punk@63: interface BRegFile;
punk@62:    method Action   wr( Rindx rindx, Bit#(32) data );
punk@63:    method ActionValue#( Bit#(32)) rd1( Rindx rindx );
punk@63:    method ActionValue#( Bit#(32)) rd2( Rindx rindx );
rlm@8: endinterface
rlm@8: 
punk@60: (* doc = "synthesis attribute ram_style mkBRegFile distributed;" *)
punk@60: (* synthesize *)
punk@63: module mkBRegFile(BRegFile);
rlm@8: 
punk@63:    LUTRAM#(Rindx, Bit#(32)) rf <- mkLUTRAMU_RegFile();
punk@63:    RWire#(Tuple2#(Rindx, Bit#(32))) rw <-mkRWire();
rlm@8: 
punk@62:    method Action wr( Rindx rindx, Bit#(32) data );
punk@62:       rf.upd( rindx, data );
punk@63:       rw.wset(tuple2(rindx,data));
rlm@8:    endmethod
rlm@8: 
punk@63:    method ActionValue#(Bit#(32)) rd1 (Rindx r);
punk@62:       if (r == 0) return 0;
punk@62:       else begin
punk@62:             case (rw.wget()) matches
punk@62: 	     tagged Valid {.wr, .d} :
punk@62: 	       return (wr == r) ? d : rf.sub(r);
punk@62: 	     tagged Invalid : return rf.sub(r);
punk@62:      	    endcase
punk@62: 	   end
punk@62:    endmethod
punk@62: 
punk@63:    method ActionValue#(Bit#(32)) rd2 (Rindx r);
punk@62:       if (r == 0) return 0;
punk@62:       else begin
punk@62:             case (rw.wget()) matches
punk@62: 	     tagged Valid {.wr, .d} :
punk@62: 	       return (wr == r) ? d : rf.sub(r);
punk@62: 	     tagged Invalid : return rf.sub(r);
punk@62:      	    endcase
punk@62: 	   end
rlm@8:    endmethod
rlm@8:    
rlm@8: endmodule