punk@13: /// The MIT License punk@13: punk@13: // Copyright (c) 2009 Massachusetts Institute of Technology punk@13: punk@13: // Permission is hereby granted, free of charge, to any person obtaining a copy punk@13: // of this software and associated documentation files (the "Software"), to deal punk@13: // in the Software without restriction, including without limitation the rights punk@13: // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell punk@13: // copies of the Software, and to permit persons to whom the Software is punk@13: // furnished to do so, subject to the following conditions: punk@13: punk@13: // The above copyright notice and this permission notice shall be included in punk@13: // all copies or substantial portions of the Software. punk@13: punk@13: // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR punk@13: // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, punk@13: // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE punk@13: // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER punk@13: // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, punk@13: // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN punk@13: // THE SOFTWARE. punk@13: punk@13: import Connectable::*; punk@13: import GetPut::*; punk@13: import ClientServer::*; punk@13: import RegFile::*; punk@13: punk@13: import FIFO::*; punk@13: import FIFOF::*; punk@13: import SFIFO::*; punk@13: import RWire::*; punk@13: punk@13: import Trace::*; punk@13: import BFIFO::*; punk@13: import MemTypes::*; punk@13: import ProcTypes::*; punk@13: import BRegFile::*; punk@13: import BranchPred::*; punk@13: //import PathTypes::*; This is only there to force the debugging punk@13: punk@13: //AWB includes punk@13: `include "asim/provides/low_level_platform_interface.bsh" punk@13: `include "asim/provides/soft_connections.bsh" punk@13: `include "asim/provides/common_services.bsh" punk@13: punk@13: // Local includes punk@13: //`include "asim/provides/processor_library.bsh" (included above directly) punk@13: `include "asim/rrr/remote_server_stub_PROCESSORSYSTEMRRR.bsh" punk@13: `include "asim/provides/common_services.bsh" punk@13: `include "asim/dict/STATS_PROCESSOR.bsh" punk@13: `include "asim/provides/audio_pipe_types.bsh" punk@13: punk@13: // Local includes. Look for the correspondingly named .awb files punk@13: // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/ punk@13: // to find the actual Bluespec files which are used to generate punk@13: // these includes. These files are specific to this audio processing punk@13: // pipeline punk@13: punk@13: `include "asim/provides/audio_processor_types.bsh" punk@13: punk@13: //interface CPUToHost; punk@13: // method Bit#(32) cpuToHost(int req); punk@13: //endinterface punk@13: punk@13: interface Proc; punk@13: punk@13: // Interface from processor to caches punk@13: interface Client#(DataReq,DataResp) dmem_client; punk@13: interface Client#(InstReq,InstResp) imem_client; punk@13: punk@13: // Interface for enabling/disabling statistics on the rest of the core punk@13: interface Get#(Bool) statsEn_get; punk@13: punk@13: // // Interface to host punk@13: // interface CPUToHost tohost; punk@13: punk@13: // Interface to Audio Pipeline punk@13: interface AudioOut audioOut; punk@13: punk@13: endinterface punk@13: punk@13: //The full interface for this is as below in the common file for audioProcessorTypes.bsv punk@13: interface AudioOut; punk@13: interface Get#(AudioProcessorUnit) audioSampleOutput; punk@13: endinterface punk@13: punk@13: //interface AudioIn; punk@13: // interface Put#(AudioProcessorUnit) audioSampleInput; punk@13: //endinterface punk@13: punk@13: typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits); punk@13: punk@13: //----------------------------------------------------------- punk@13: // Register file module punk@13: //----------------------------------------------------------- punk@13: punk@13: interface BRFile; punk@13: method Action wr( Rindx rindx, Bit#(32) data ); punk@13: method Bit#(32) rd1( Rindx rindx ); punk@13: method Bit#(32) rd2( Rindx rindx ); punk@13: endinterface punk@13: punk@13: module mkBRFile( BRFile ); punk@13: punk@13: RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile(); punk@13: punk@13: method Action wr( Rindx rindx, Bit#(32) data ); punk@13: rfile.upd( rindx, data ); punk@13: endmethod punk@13: punk@13: method Bit#(32) rd1( Rindx rindx ); punk@13: return ( rindx == 0 ) ? 0 : rfile.sub(rindx); punk@13: endmethod punk@13: punk@13: method Bit#(32) rd2( Rindx rindx ); punk@13: return ( rindx == 0 ) ? 0 : rfile.sub(rindx); punk@13: endmethod punk@13: punk@13: endmodule punk@13: punk@13: //----------------------------------------------------------- punk@13: // Helper functions punk@13: //----------------------------------------------------------- punk@13: punk@13: function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 ); punk@13: return zeroExtend( pack( signedLT(val1,val2) ) ); punk@13: endfunction punk@13: punk@13: function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 ); punk@13: return zeroExtend( pack( val1 < val2 ) ); punk@13: endfunction punk@13: punk@13: function Bit#(32) rshft( Bit#(32) val ); punk@13: return zeroExtend(val[4:0]); punk@13: endfunction punk@13: punk@13: punk@13: //----------------------------------------------------------- punk@13: // Find funct for wbQ punk@13: //----------------------------------------------------------- punk@13: function Bool findwbf(Rindx fVal, WBResult cmpVal); punk@13: case (cmpVal) matches punk@13: tagged WB_ALU {data:.res, dest:.rd} : punk@13: return (fVal == rd); punk@13: tagged WB_Load .rd : punk@13: return (fVal == rd); punk@13: tagged WB_Store .st : punk@13: return False; punk@13: tagged WB_Host .x : punk@13: return False; punk@13: endcase punk@13: endfunction punk@13: punk@13: punk@13: //----------------------------------------------------------- punk@13: // Stall funct for wbQ punk@13: //----------------------------------------------------------- punk@13: function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f); punk@13: case (inst) matches punk@13: // -- Memory Ops ------------------------------------------------ punk@13: tagged LW .it : punk@13: return f.find(it.rbase); punk@13: tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} : punk@13: return (f.find(addr) || f.find2(dreg)); punk@13: punk@13: // -- Simple Ops ------------------------------------------------ punk@13: tagged ADDIU .it : return f.find(it.rsrc); punk@13: tagged SLTI .it : return f.find(it.rsrc); punk@13: tagged SLTIU .it : return f.find(it.rsrc); punk@13: tagged ANDI .it : return f.find(it.rsrc); punk@13: tagged ORI .it : return f.find(it.rsrc); punk@13: tagged XORI .it : return f.find(it.rsrc); punk@13: punk@13: tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself punk@13: tagged SLL .it : return f.find(it.rsrc); punk@13: tagged SRL .it : return f.find(it.rsrc); punk@13: tagged SRA .it : return f.find(it.rsrc); punk@13: tagged SLLV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); punk@13: tagged SRLV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); punk@13: tagged SRAV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); punk@13: tagged ADDU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); punk@13: tagged SUBU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); punk@13: tagged AND .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); punk@13: tagged OR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); punk@13: tagged XOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); punk@13: tagged NOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); punk@13: tagged SLT .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); punk@13: tagged SLTU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); punk@13: punk@13: punk@13: // -- Branches -------------------------------------------------- punk@13: punk@13: tagged BLEZ .it : return (f.find(it.rsrc)); punk@13: tagged BGTZ .it : return (f.find(it.rsrc)); punk@13: tagged BLTZ .it : return (f.find(it.rsrc)); punk@13: tagged BGEZ .it : return (f.find(it.rsrc)); punk@13: tagged BEQ .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); punk@13: tagged BNE .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); punk@13: punk@13: // -- Jumps ----------------------------------------------------- punk@13: punk@13: tagged J .it : return False; punk@13: tagged JR .it : return f.find(it.rsrc); punk@13: tagged JALR .it : return f.find(it.rsrc); punk@13: tagged JAL .it : return False; punk@13: punk@13: // -- Cop0 ------------------------------------------------------ punk@13: punk@13: tagged MTC0 .it : return f.find(it.rsrc); punk@13: tagged MFC0 .it : return False; punk@13: punk@13: // -- Illegal --------------------------------------------------- punk@13: punk@13: default : return False; punk@13: punk@13: endcase punk@13: endfunction punk@13: //----------------------------------------------------------- punk@13: // Reference processor punk@13: //----------------------------------------------------------- punk@13: punk@13: punk@13: //(* doc = "synthesis attribute ram_style mkProc distributed;" *) punk@13: //(* synthesize *) punk@13: punk@13: module [CONNECTED_MODULE] mkProc( Proc ); punk@13: punk@13: //----------------------------------------------------------- punk@13: // Debug port punk@13: punk@13: ServerStub_PROCESSORSYSTEMRRR server_stub <- mkServerStub_PROCESSORSYSTEMRRR(); punk@13: punk@13: punk@13: //----------------------------------------------------------- punk@13: // State punk@13: punk@13: // Standard processor state punk@13: punk@13: Reg#(Addr) pc <- mkReg(32'h00001000); punk@13: Reg#(Epoch) epoch <- mkReg(0); punk@13: Reg#(Stage) stage <- mkReg(PCgen); punk@13: BRFile rf <- mkBRFile; punk@13: punk@13: // Branch Prediction punk@13: BranchPred bp <- mkBranchPred(); punk@13: FIFO#(PCStat) execpc <- mkLFIFO(); punk@13: punk@13: // Pipelines punk@13: FIFO#(PCStat) pcQ <-mkSizedFIFO(3); punk@13: SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf); punk@13: punk@13: Reg#(Bit#(32)) cp0_tohost <- mkReg(0); punk@13: Reg#(Bit#(32)) cp0_fromhost <- mkReg(0); punk@13: Reg#(Bool) cp0_statsEn <- mkReg(False); punk@13: punk@13: // Memory request/response state punk@13: punk@13: FIFO#(InstReq) instReqQ <- mkBFIFO1(); punk@13: FIFO#(InstResp) instRespQ <- mkFIFO(); punk@13: punk@13: FIFO#(DataReq) dataReqQ <- mkBFIFO1(); punk@13: FIFO#(DataResp) dataRespQ <- mkFIFO(); punk@13: punk@13: // Audio I/O punk@13: FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO; punk@13: FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO; punk@13: punk@13: punk@13: // Statistics state (2010) punk@13: // Reg#(Stat) num_cycles <- mkReg(0); punk@13: // Reg#(Stat) num_inst <- mkReg(0); punk@13: punk@13: //Or: punk@13: // Statistics state punk@13: STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT); punk@13: STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT); punk@13: punk@13: //----------------------------------------------------------- punk@13: // Rules punk@13: punk@13: (* descending_urgency = "exec, pcgen" *) punk@13: rule pcgen; //( stage == PCgen ); punk@13: let pc_plus4 = pc + 4; punk@13: punk@13: traceTiny("mkProc", "pc",pc); punk@13: traceTiny("mkProc", "pcgen","P"); punk@13: instReqQ.enq( LoadReq{ addr:pc, tag:epoch} ); punk@13: punk@13: let next_pc = bp.get(pc); punk@13: if (next_pc matches tagged Valid .npc) punk@13: begin punk@13: pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch}); punk@13: pc <= npc; punk@13: end punk@13: else punk@13: begin punk@13: pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch}); punk@13: pc <= pc_plus4; punk@13: end punk@13: punk@13: endrule punk@13: punk@13: rule discard (instRespQ.first() matches tagged LoadResp .ld punk@13: &&& ld.tag != epoch); punk@13: traceTiny("mkProc", "stage", "D"); punk@13: instRespQ.deq(); punk@13: endrule punk@13: punk@13: (* conflict_free = "exec, writeback" *) punk@13: rule exec (instRespQ.first() matches tagged LoadResp.ld punk@13: &&& (ld.tag == epoch) punk@13: &&& unpack(ld.data) matches .inst punk@13: &&& !stall(inst, wbQ)); punk@13: punk@13: // Some abbreviations punk@13: let sext = signExtend; punk@13: let zext = zeroExtend; punk@13: let sra = signedShiftRight; punk@13: punk@13: // Get the instruction punk@13: punk@13: instRespQ.deq(); punk@13: Instr inst punk@13: = case ( instRespQ.first() ) matches punk@13: tagged LoadResp .ld : return unpack(ld.data); punk@13: tagged StoreResp .st : return ?; punk@13: endcase; punk@13: punk@13: // Get the PC info punk@13: let instrpc = pcQ.first().qpc; punk@13: let pc_plus4 = instrpc + 4; punk@13: punk@13: Bool branchTaken = False; punk@13: Addr newPC = pc_plus4; punk@13: punk@13: // Tracing punk@13: traceTiny("mkProc", "exec","X"); punk@13: traceTiny("mkProc", "exInstTiny",inst); punk@13: traceFull("mkProc", "exInstFull",inst); punk@13: punk@13: case ( inst ) matches punk@13: punk@13: // -- Memory Ops ------------------------------------------------ punk@13: punk@13: tagged LW .it : punk@13: begin punk@13: Addr addr = rf.rd1(it.rbase) + sext(it.offset); punk@13: dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } ); punk@13: wbQ.enq(tagged WB_Load it.rdst); punk@13: end punk@13: punk@13: tagged SW .it : punk@13: begin punk@13: Addr addr = rf.rd1(it.rbase) + sext(it.offset); punk@13: dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } ); punk@13: wbQ.enq(tagged WB_Store); punk@13: end punk@13: punk@13: // -- Simple Ops ------------------------------------------------ punk@13: punk@13: tagged ADDIU .it : punk@13: begin punk@13: Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm); punk@13: wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst}); punk@13: end punk@13: tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )}); punk@13: tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) }); punk@13: tagged ANDI .it : punk@13: begin punk@13: Bit#(32) zext_it_imm = zext(it.imm); punk@13: wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} ); punk@13: end punk@13: tagged ORI .it : punk@13: begin punk@13: Bit#(32) zext_it_imm = zext(it.imm); punk@13: wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} ); punk@13: end punk@13: tagged XORI .it : punk@13: begin punk@13: Bit#(32) zext_it_imm = zext(it.imm); punk@13: wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )}); punk@13: end punk@13: tagged LUI .it : punk@13: begin punk@13: Bit#(32) zext_it_imm = zext(it.imm); punk@13: wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) }); punk@13: end punk@13: punk@13: tagged SLL .it : punk@13: begin punk@13: Bit#(32) zext_it_shamt = zext(it.shamt); punk@13: wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} ); punk@13: end punk@13: tagged SRL .it : punk@13: begin punk@13: Bit#(32) zext_it_shamt = zext(it.shamt); punk@13: wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )}); punk@13: end punk@13: tagged SRA .it : punk@13: begin punk@13: Bit#(32) zext_it_shamt = zext(it.shamt); punk@13: wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )}); punk@13: end punk@13: tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )}); punk@13: tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} ); punk@13: tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) }); punk@13: tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} ); punk@13: tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} ); punk@13: tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} ); punk@13: tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} ); punk@13: tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} ); punk@13: tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} ); punk@13: tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) }); punk@13: tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) }); punk@13: punk@13: // -- Branches -------------------------------------------------- punk@13: punk@13: tagged BLEZ .it : punk@13: if ( signedLE( rf.rd1(it.rsrc), 0 ) ) punk@13: begin punk@13: newPC = pc_plus4 + (sext(it.offset) << 2); punk@13: branchTaken = True; punk@13: end punk@13: punk@13: tagged BGTZ .it : punk@13: if ( signedGT( rf.rd1(it.rsrc), 0 ) ) punk@13: begin punk@13: newPC = pc_plus4 + (sext(it.offset) << 2); punk@13: branchTaken = True; punk@13: end punk@13: punk@13: tagged BLTZ .it : punk@13: if ( signedLT( rf.rd1(it.rsrc), 0 ) ) punk@13: begin punk@13: newPC = pc_plus4 + (sext(it.offset) << 2); punk@13: branchTaken = True; punk@13: end punk@13: punk@13: tagged BGEZ .it : punk@13: if ( signedGE( rf.rd1(it.rsrc), 0 ) ) punk@13: begin punk@13: newPC = pc_plus4 + (sext(it.offset) << 2); punk@13: branchTaken = True; punk@13: end punk@13: punk@13: tagged BEQ .it : punk@13: if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) ) punk@13: begin punk@13: newPC = pc_plus4 + (sext(it.offset) << 2); punk@13: branchTaken = True; punk@13: end punk@13: punk@13: tagged BNE .it : punk@13: if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) ) punk@13: begin punk@13: newPC = pc_plus4 + (sext(it.offset) << 2); punk@13: branchTaken = True; punk@13: end punk@13: punk@13: // -- Jumps ----------------------------------------------------- punk@13: punk@13: tagged J .it : punk@13: begin punk@13: newPC = { pc_plus4[31:28], it.target, 2'b0 }; punk@13: branchTaken = True; punk@13: end punk@13: punk@13: tagged JR .it : punk@13: begin punk@13: newPC = rf.rd1(it.rsrc); punk@13: branchTaken = True; punk@13: end punk@13: punk@13: tagged JAL .it : punk@13: begin punk@13: wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 }); punk@13: newPC = { pc_plus4[31:28], it.target, 2'b0 }; punk@13: branchTaken = True; punk@13: end punk@13: punk@13: tagged JALR .it : punk@13: begin punk@13: wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 }); punk@13: newPC = rf.rd1(it.rsrc); punk@13: branchTaken = True; punk@13: end punk@13: punk@13: // -- Cop0 ------------------------------------------------------ punk@13: punk@13: tagged MTC0 .it : punk@13: begin punk@13: case ( it.cop0dst ) punk@13: 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc))); punk@13: 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc)); punk@13: default : punk@13: $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" ); punk@13: endcase punk@13: wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be. punk@13: end punk@13: punk@13: //this is host stuff? punk@13: tagged MFC0 .it : punk@13: begin punk@13: case ( it.cop0src ) punk@13: // not actually an ALU instruction but don't have the format otherwise punk@13: 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) }); punk@13: 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost }); punk@13: 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost }); punk@13: default : punk@13: $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" ); punk@13: endcase punk@13: end punk@13: punk@13: // -- Illegal --------------------------------------------------- punk@13: punk@13: default : punk@13: $display( " RTL-ERROR : %m : Illegal instruction !" ); punk@13: punk@13: endcase punk@13: punk@13: //evaluate branch prediction punk@13: Addr ppc = pcQ.first().qnxtpc; //predicted branch punk@13: if (ppc != newPC) //prediction wrong punk@13: begin punk@13: epoch <= pcQ.first().qepoch + 1; punk@13: bp.upd(instrpc, newPC); //update branch predictor punk@13: pcQ.clear(); punk@13: pc <= newPC; punk@13: end punk@13: else punk@13: pcQ.deq(); punk@13: punk@13: if ( cp0_statsEn ) punk@13: num_inst.incr(); punk@13: punk@13: endrule punk@13: punk@13: rule writeback; // ( stage == Writeback ); punk@13: traceTiny("mkProc", "writeback","W"); punk@13: punk@13: punk@13: // get what to do off the writeback queue punk@13: wbQ.deq(); punk@13: case (wbQ.first()) matches punk@13: tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res); punk@13: tagged WB_Load .regWr : punk@13: begin punk@13: dataRespQ.deq(); punk@13: if (dataRespQ.first() matches tagged LoadResp .ld) punk@13: rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate? punk@13: end punk@13: tagged WB_Store : dataRespQ.deq(); punk@13: tagged WB_Host .dat : noAction; punk@13: endcase punk@13: punk@13: endrule punk@13: punk@13: rule inc_num_cycles; punk@13: if ( cp0_statsEn ) punk@13: num_cycles.incr(); punk@13: endrule punk@13: punk@13: (* conservative_implicit_conditions *) punk@13: rule handleCPUToHost; punk@13: let req <- server_stub.acceptRequest_ReadCPUToHost(); punk@13: case (req) punk@13: 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost); punk@13: 1: server_stub.sendResponse_ReadCPUToHost(pc); punk@13: 2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage))); punk@13: endcase punk@13: endrule punk@13: punk@13: // for now, we don't do anything. punk@13: rule connectAudioReqResp; punk@13: $display("FIR copies a data"); punk@13: outAudioFifo.enq(inAudioFifo.first); punk@13: outAudioFifo.deq; punk@13: endrule punk@13: punk@13: // Server items & rules: punk@13: punk@13: rule feedInput; punk@13: let command <- server_stub.acceptRequest_SendUnprocessedStream(); punk@13: AudioProcessorControl ctrl = unpack(truncate(command.ctrl)); punk@13: punk@13: if(ctrl == EndOfFile) punk@13: begin punk@13: inAudioFifo.enq(tagged EndOfFile); punk@13: end punk@13: else punk@13: begin punk@13: inAudioFifo.enq(tagged Sample unpack(truncate(command.sample))); punk@13: end punk@13: endrule punk@13: punk@13: punk@13: //----------------------------------------------------------- punk@13: // Methods punk@13: punk@13: interface Client imem_client; punk@13: interface Get request = toGet(instReqQ); punk@13: interface Put response = toPut(instRespQ); punk@13: endinterface punk@13: punk@13: interface Client dmem_client; punk@13: interface Get request = toGet(dataReqQ); punk@13: interface Put response = toPut(dataRespQ); punk@13: endinterface punk@13: punk@13: interface Get statsEn_get = toGet(asReg(cp0_statsEn)); punk@13: punk@13: // interface CPUToHost tohost; punk@13: // method Bit#(32) cpuToHost(int req); punk@13: // return (case (req) punk@13: // 0: cp0_tohost; punk@13: // 1: pc; punk@13: // 2: zeroExtend(pack(stage)); punk@13: // endcase); punk@13: // endmethod punk@13: // endinterface punk@13: punk@13: interface AudioOut audio; punk@13: interface audioSampleOutput = fifoToGet(outAudioFifo); punk@13: endinterface punk@13: punk@13: punk@13: endmodule punk@13: