rlm@8: // The MIT License
rlm@8: 
rlm@8: // Copyright (c) 2009 Massachusetts Institute of Technology
rlm@8: 
rlm@8: // Permission is hereby granted, free of charge, to any person obtaining a copy
rlm@8: // of this software and associated documentation files (the "Software"), to deal
rlm@8: // in the Software without restriction, including without limitation the rights
rlm@8: // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
rlm@8: // copies of the Software, and to permit persons to whom the Software is
rlm@8: // furnished to do so, subject to the following conditions:
rlm@8: 
rlm@8: // The above copyright notice and this permission notice shall be included in
rlm@8: // all copies or substantial portions of the Software.
rlm@8: 
rlm@8: // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
rlm@8: // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
rlm@8: // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
rlm@8: // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
rlm@8: // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
rlm@8: // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
rlm@8: // THE SOFTWARE.
rlm@8: 
rlm@8: import Connectable::*;
rlm@8: import GetPut::*;
rlm@8: import ClientServer::*;
rlm@8: import FIFO::*;
rlm@8: import SpecialFIFOs::*;
rlm@8: 
rlm@8: //AWB includes
rlm@8: `include "asim/provides/low_level_platform_interface.bsh"
rlm@8: `include "asim/provides/soft_connections.bsh"
rlm@8: `include "asim/provides/common_services.bsh"
rlm@8: 
rlm@8: 
rlm@8: // Local includes
rlm@8: `include "asim/provides/core.bsh"
rlm@8: `include "asim/provides/processor_library.bsh"
rlm@8: `include "asim/provides/processor_library.bsh"
rlm@8: `include "asim/provides/fpga_components.bsh"
rlm@8: `include "asim/rrr/remote_client_stub_PROCESSORSYSTEMRRR.bsh"
rlm@8: 
rlm@8: module [CONNECTED_MODULE] mkConnectedApplication ();
rlm@8: 
rlm@8:   Core core <- mkCore;
rlm@8:   Reg#(int) cycle <- mkReg(0);
rlm@8: 
rlm@8:   //External memory 
rlm@8:   // I'm not comfortable assuming that the memory subsystem is in order  
rlm@8:   // So I'll insert a completion buffer here.  
rlm@8:   ClientStub_PROCESSORSYSTEMRRR client_stub <- mkClientStub_PROCESSORSYSTEMRRR();   
rlm@8:   // Make this big enough so that several outstanding requests may be supported
rlm@8:   FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
rlm@8: 
rlm@8:   // this is for the tracing
rlm@8:   rule printCycles;
rlm@8:     cycle <= cycle+1;
rlm@8:     $fdisplay(stderr, " => Cycle = %d", cycle);
rlm@8:   endrule
rlm@8: 
rlm@8: 
rlm@8:   rule sendMemReq;
rlm@8:     let coreReq <- core.mmem_client.request.get;
rlm@8:     case (coreReq) matches 
rlm@8:       tagged LoadReq .load: begin
rlm@8:                               //Allocate ROB space
rlm@8:                               client_stub.makeRequest_MemoryRequestLoad(load.addr);
rlm@8:                               tags.enq(load.tag);
rlm@8:                             end
rlm@8:       tagged StoreReq .store: begin
rlm@8:                                 client_stub.makeRequest_MemoryRequestStore(store.addr,store.data);
rlm@8:                               end
rlm@8:     endcase
rlm@8:   endrule
rlm@8:   
rlm@8:   rule receiveMemResp;
rlm@8:     let memResp <- client_stub.getResponse_MemoryRequestLoad();
rlm@8:     tags.deq;
rlm@8:     core.mmem_client.response.put(tagged LoadResp {data:memResp,
rlm@8:                                                    tag: tags.first});
rlm@8:   endrule
rlm@8: 
rlm@8: endmodule