punk@13: // The MIT License punk@13: punk@13: // Copyright (c) 2009 Massachusetts Institute of Technology punk@13: punk@13: // Permission is hereby granted, free of charge, to any person obtaining a copy punk@13: // of this software and associated documentation files (the "Software"), to deal punk@13: // in the Software without restriction, including without limitation the rights punk@13: // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell punk@13: // copies of the Software, and to permit persons to whom the Software is punk@13: // furnished to do so, subject to the following conditions: punk@13: punk@13: // The above copyright notice and this permission notice shall be included in punk@13: // all copies or substantial portions of the Software. punk@13: punk@13: // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR punk@13: // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, punk@13: // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE punk@13: // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER punk@13: // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, punk@13: // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN punk@13: // THE SOFTWARE. punk@13: punk@13: // Author: Kermin Fleming kfleming@mit.edu punk@13: punk@13: import Connectable::*; punk@13: import GetPut::*; punk@13: import ClientServer::*; punk@13: import FIFO::*; punk@15: import SpecialFIFOs::*; punk@13: punk@13: //AWB includes punk@13: `include "asim/provides/low_level_platform_interface.bsh" punk@13: `include "asim/provides/soft_connections.bsh" punk@13: `include "asim/provides/common_services.bsh" punk@13: punk@13: //Local includes punk@13: `include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface punk@33: `include "asim/provides/path_types.bsh" punk@13: `include "asim/provides/core.bsh" punk@43: `include "asim/provides/mixer.bsh" punk@15: `include "asim/provides/processor_library.bsh" punk@15: `include "asim/provides/fpga_components.bsh" punk@33: `include "asim/provides/scratchpad_memory.bsh" punk@33: `include "asim/provides/mem_services.bsh" punk@33: `include "asim/dict/VDEV_SCRATCH.bsh" punk@33: punk@13: `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh" punk@36: `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh" punk@13: punk@13: module [CONNECTED_MODULE] mkConnectedApplication (); punk@13: Core core <- mkCore; rlm@47: // RLM:: rlm@47: // the simple existance of this additional core causes the dreaded rlm@47: // beast to emerge --- the ASSERTION FAILURE: sw/model/stats-device.cpp:317 Cycle:0 rlm@47: //stats device: Duplicate entry DATA_CACHE_NUM_WRITEBACKS, postion 0 rlm@47: //Core core1 <- mkCore; punk@13: Reg#(int) cycle <- mkReg(0); punk@13: punk@39: // Reg#(Bit#(32)) ac_fini <- mkReg(0); punk@39: punk@13: //External memory punk@13: // I'm not comfortable assuming that the memory subsystem is in order punk@33: // So I'll insert a completion buffer here. punk@33: MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED); //Services Memory items punk@33: punk@33: // Services Samples punk@15: ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR(); punk@13: // Make this big enough so that several outstanding requests may be supported punk@13: FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8); punk@13: punk@36: //----------------------------------------------------------- punk@36: // Debug port punk@36: punk@36: ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR(); punk@36: punk@36: punk@13: // this is for the tracing punk@13: rule printCycles; punk@13: cycle <= cycle+1; punk@13: $fdisplay(stderr, " => Cycle = %d", cycle); punk@13: endrule punk@13: punk@13: rule sendMemReq; punk@13: let coreReq <- core.mmem_client.request.get; punk@13: case (coreReq) matches punk@13: tagged LoadReq .load: begin punk@43: // $display("PIPE Load Addr Req %h", load.addr); punk@13: //Allocate ROB space punk@33: memory.readReq(truncate(load.addr>>2)); punk@13: tags.enq(load.tag); punk@13: end punk@42: tagged StoreReq .store: begin punk@43: // $display("PIPE Write Addr Req %h", store.addr); punk@33: memory.write(truncate(store.addr>>2),store.data); punk@13: end punk@13: endcase punk@13: endrule punk@13: punk@13: rule receiveMemResp; punk@33: let memResp <- memory.readRsp(); punk@13: tags.deq; punk@13: core.mmem_client.response.put(tagged LoadResp {data:memResp, punk@13: tag: tags.first}); punk@43: // $display("PIPE Receive MemReq %x", memResp); punk@13: endrule punk@13: punk@13: rule feedOutput; punk@13: let pipelineData <- core.sampleOutput.get(); punk@13: AudioProcessorControl endOfFileTag = EndOfFile; punk@13: AudioProcessorControl sampleTag = Data; punk@13: punk@25: case (pipelineData) matches punk@25: tagged EndOfFile: punk@15: client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?); punk@25: tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)), zeroExtend(pack(sample))); punk@25: endcase punk@13: endrule punk@13: punk@36: //***** SERVER Side ***** punk@36: punk@39: /* (* conservative_implicit_conditions *) punk@37: rule handleCPUToHost; punk@37: let req <- server_stub.acceptRequest_ReadCPUToHost(); punk@37: case (req) punk@37: 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost); punk@37: endcase punk@37: endrule punk@39: */ punk@36: rule feedInput; punk@36: let command <- server_stub.acceptRequest_SendUnprocessedStream(); punk@36: AudioProcessorControl ctrl = unpack(truncate(command.ctrl)); rlm@41: rlm@41: Bit#(32) test = unpack(truncate(command.channel)); rlm@41: $display("rlm: %x", test); rlm@41: rlm@41: rlm@41: if(ctrl == EndOfFile) punk@36: begin punk@43: $display("lsp: PIPE received EOF "); punk@43: core.sampleInput.put(tagged EndOfFile); punk@36: end punk@36: else punk@36: begin punk@43: // $display("lsp: PIPE received Data "); punk@43: core.sampleInput.put(tagged Sample unpack(truncate(command.sample))); punk@36: end punk@36: endrule punk@13: endmodule