punk@13: // The MIT License
punk@13: 
punk@13: // Copyright (c) 2009 Massachusetts Institute of Technology
punk@13: 
punk@13: // Permission is hereby granted, free of charge, to any person obtaining a copy
punk@13: // of this software and associated documentation files (the "Software"), to deal
punk@13: // in the Software without restriction, including without limitation the rights
punk@13: // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
punk@13: // copies of the Software, and to permit persons to whom the Software is
punk@13: // furnished to do so, subject to the following conditions:
punk@13: 
punk@13: // The above copyright notice and this permission notice shall be included in
punk@13: // all copies or substantial portions of the Software.
punk@13: 
punk@13: // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
punk@13: // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
punk@13: // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
punk@13: // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
punk@13: // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
punk@13: // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
punk@13: // THE SOFTWARE.
punk@13: 
punk@13: import Connectable::*;
punk@13: import GetPut::*;
punk@13: import ClientServer::*;
punk@13: import Processor::*;
punk@13: import MemArb::*;
punk@13: import MemTypes::*;
punk@48: import FIFO::*;
punk@13: 
punk@13: //AWB includes
punk@13: `include "asim/provides/low_level_platform_interface.bsh"
punk@13: `include "asim/provides/soft_connections.bsh"
punk@13: `include "asim/provides/common_services.bsh"
punk@13: 
punk@13: // Local includes
punk@13: `include "asim/provides/processor_library.bsh"
punk@13: `include "asim/provides/mem_arb.bsh"
punk@13: `include "asim/provides/instruction_cache.bsh"
punk@13: `include "asim/provides/data_cache.bsh"
punk@13: `include "asim/provides/processor.bsh"
punk@15: `include "asim/provides/audio_pipe_types.bsh"
punk@15: 
punk@48: // Scratchpad includes
punk@48: `include "asim/provides/scratchpad_memory.bsh"
punk@48: `include "asim/provides/mem_services.bsh"
punk@48: `include "asim/dict/VDEV_SCRATCH.bsh"
punk@48: 
punk@21: interface Core;
punk@13: 
punk@15:    interface Get#(AudioProcessorUnit) sampleOutput;
punk@36:    interface Put#(AudioProcessorUnit) sampleInput;
punk@36: 	 
punk@36: //   interface CPUToHost tohost;
punk@36:    
punk@13: endinterface
punk@13: 
punk@21: module   [CONNECTED_MODULE]  mkCore( Core );
punk@48:    
punk@13: 
punk@13:   // Instantiate the modules
punk@13: 
punk@13:   Proc proc <- mkProc();
punk@13:   ICache#(InstReq,InstResp) icache <- mkInstCache();
punk@13:   DCache#(DataReq,DataResp) dcache <- mkDataCache();
punk@13:   MemArb marb <- mkMemArb();
punk@48:   MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED);   //Services Memory items
punk@13: 
punk@48:   // Make this big enough so that several outstanding requests may be supported
punk@48:   FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
punk@48:    
punk@13:   // Internal connections
punk@13: 
punk@13:   mkConnection( proc.statsEn_get,   icache.statsEn_put );
punk@13:   mkConnection( proc.statsEn_get,   dcache.statsEn_put );
punk@26:   mkConnection( proc.imem_client,   icache.proc_server );
punk@26:   mkConnection( proc.dmem_client,   dcache.proc_server );
punk@13:   mkConnection( icache.mmem_client, marb.cache0_server );
punk@13:   mkConnection( dcache.mmem_client, marb.cache1_server );
punk@13: 
punk@48:   // Memory Access
punk@48:   rule sendMemReq;
punk@48:     let coreReq <- marb.mmem_client.request.get;
punk@48:     case (coreReq) matches 
punk@48:       tagged LoadReq .load: begin
punk@48: //	                      $display("PIPE Load Addr Req %h", load.addr); 
punk@48:                               //Allocate ROB space
punk@48:                               memory.readReq(truncate(load.addr>>2));
punk@48:                               tags.enq(load.tag);
punk@48:                             end
punk@48:       tagged StoreReq .store: begin
punk@48: //	  	              $display("PIPE Write Addr Req %h", store.addr); 
punk@48: 	                      memory.write(truncate(store.addr>>2),store.data);
punk@48:                               end
punk@48:     endcase
punk@48:   endrule
punk@48:   
punk@48:   rule receiveMemResp;
punk@48:     let memResp <- memory.readRsp();
punk@48:     tags.deq;
punk@48:     marb.mmem_client.response.put(tagged LoadResp {data:memResp,
punk@48:                                                    tag: tags.first});
punk@48: //   	                $display("PIPE Receive MemReq %x", memResp); 
punk@48:   endrule
punk@48: 
punk@13:   // Methods
punk@48:      
punk@15:    interface sampleOutput = proc.sampleOutput;
punk@36:    interface sampleInput = proc.sampleInput;
punk@36: 
punk@36: //   interface CPUToHost tohost = proc.tohost;
punk@13: 
punk@13: endmodule