punk@1: signature Bridge where {
punk@1: import ¶Assert®¶;
punk@1: 		
punk@1: import ¶ConfigReg®¶;
punk@1: 		   
punk@1: import ¶Counter®¶;
punk@1: 		 
punk@1: import ¶DReg®¶;
punk@1: 	      
punk@1: import ¶EdgeDetect®¶;
punk@1: 		    
punk@1: import ¶FIFOF_®¶;
punk@1: 		
punk@1: import ¶FIFOF®¶;
punk@1: 	       
punk@1: import ¶FIFO®¶;
punk@1: 	      
punk@1: import ¶HList®¶;
punk@1: 	       
punk@1: import ¶Inout®¶;
punk@1: 	       
punk@1: import ¶List®¶;
punk@1: 	      
punk@1: import BFIFO;
punk@1: 	    
punk@1: import ¶Clocks®¶;
punk@1: 		
punk@1: import ¶DiniPCIE®¶;
punk@1: 		  
punk@1: import ¶ListN®¶;
punk@1: 	       
punk@1: import ¶ModuleContextCore®¶;
punk@1: 			   
punk@1: import ¶ModuleContext®¶;
punk@1: 		       
punk@1: import ¶Monad®¶;
punk@1: 	       
punk@1: import ¶PrimArray®¶;
punk@1: 		   
punk@1: import ¶RWire®¶;
punk@1: 	       
punk@1: import ¶RegFile®¶;
punk@1: 		 
punk@1: import ¶Real®¶;
punk@1: 	      
punk@1: import ¶RevertingVirtualReg®¶;
punk@1: 			     
punk@1: import ¶Reserved®¶;
punk@1: 		  
punk@1: import SFIFO;
punk@1: 	    
punk@1: import ¶Vector®¶;
punk@1: 		
punk@1: import ¶BRAMCore®¶;
punk@1: 		  
punk@1: import ¶BUtils®¶;
punk@1: 		
punk@1: import ¶Connectable®¶;
punk@1: 		     
punk@1: import ¶DefaultValue®¶;
punk@1: 		      
punk@1: import ¶Gearbox®¶;
punk@1: 		 
punk@1: import ¶GetPut®¶;
punk@1: 		
punk@1: import ¶AlignedFIFOs®¶;
punk@1: 		      
punk@1: import ¶ClientServer®¶;
punk@1: 		      
punk@1: import ¶FIFOLevel®¶;
punk@1: 		   
punk@1: import ¶SceMiDefines®¶;
punk@1: 		      
punk@1: import ¶SceMiProxies®¶;
punk@1: 		      
punk@1: import ¶SpecialFIFOs®¶;
punk@1: 		      
punk@1: import ¶SceMiInternals®¶;
punk@1: 			
punk@1: import ¶SceMiAldecMacros®¶;
punk@1: 			  
punk@1: import ¶SceMiEveMacros®¶;
punk@1: 			
punk@1: import ¶SceMiMacros®¶;
punk@1: 		     
punk@1: import ¶TieOff®¶;
punk@1: 		
punk@1: import Trace;
punk@1: 	    
punk@1: import MemTypes;
punk@1: 	       
punk@1: import MemArb;
punk@1: 	     
punk@1: import ProcTypes;
punk@1: 		
punk@1: import BRegFile;
punk@1: 	       
punk@1: import BranchPred;
punk@1: 		 
punk@1: import DataCacheBlocking;
punk@1: 			
punk@1: import InstCacheBlocking;
punk@1: 			
punk@1: import Processor;
punk@1: 		
punk@1: import Core;
punk@1: 	   
punk@1: import ¶UnitAppendList®¶;
punk@1: 			
punk@1: import ¶XilinxCells®¶;
punk@1: 		     
punk@1: import ¶SceMiClocks®¶;
punk@1: 		     
punk@1: import ¶SceMiDiniPCIE®¶;
punk@1: 		       
punk@1: import ¶SceMiTCP®¶;
punk@1: 		  
punk@1: import ¶XilinxPCIE®¶;
punk@1: 		    
punk@1: import ¶SceMiVirtex5PCIE®¶;
punk@1: 			  
punk@1: import ¶SceMiPCIE®¶;
punk@1: 		   
punk@1: import ¶SceMiCore®¶;
punk@1: 		   
punk@1: import ¶SceMiXactors®¶;
punk@1: 		      
punk@1: import ¶SceMiSerialProbe®¶;
punk@1: 			  
punk@1: import ¶SceMi®¶;
punk@1: 	       
punk@1: import SceMiLayer;
punk@1: 		 
punk@1: Bridge.lt :: ¶SceMiDefines®¶.¶SceMiLinkType®¶;
punk@1: 					     
punk@1: Bridge.mkBridge :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ ¶Prelude®¶.¶Empty®¶
punk@1: }