rlm@8: 
rlm@8: import Trace::*;
rlm@8: 
rlm@8: //----------------------------------------------------------------------
rlm@8: // Other typedefs
rlm@8: //----------------------------------------------------------------------
rlm@8: 
rlm@8: typedef Bit#(32) Addr;
rlm@8: 
rlm@8: //----------------------------------------------------------------------
rlm@8: // Basic instruction type
rlm@8: //----------------------------------------------------------------------
rlm@8: 
rlm@8: typedef Bit#(5)  Rindx;
rlm@8: typedef Bit#(16) Simm;
rlm@8: typedef Bit#(16) Zimm;
rlm@8: typedef Bit#(5)  Shamt;
rlm@8: typedef Bit#(26) Target;
rlm@8: typedef Bit#(5)  CP0indx;
rlm@8: 
rlm@8: typedef union tagged                
rlm@8: {
rlm@8: 
rlm@8:   struct { Rindx rbase; Rindx rdst;  Simm offset;  } LW;
rlm@8:   struct { Rindx rbase; Rindx rsrc;  Simm offset;  } SW; 
rlm@8: 
rlm@8:   struct { Rindx rsrc;  Rindx rdst;  Simm imm;     } ADDIU;
rlm@8:   struct { Rindx rsrc;  Rindx rdst;  Simm imm;     } SLTI;
rlm@8:   struct { Rindx rsrc;  Rindx rdst;  Simm imm;     } SLTIU;
rlm@8:   struct { Rindx rsrc;  Rindx rdst;  Zimm imm;     } ANDI;
rlm@8:   struct { Rindx rsrc;  Rindx rdst;  Zimm imm;     } ORI;
rlm@8:   struct { Rindx rsrc;  Rindx rdst;  Zimm imm;     } XORI;
rlm@8:   struct {              Rindx rdst;  Zimm imm;     } LUI;
rlm@8: 
rlm@8:   struct { Rindx rsrc;  Rindx rdst;  Shamt shamt;  } SLL;
rlm@8:   struct { Rindx rsrc;  Rindx rdst;  Shamt shamt;  } SRL;
rlm@8:   struct { Rindx rsrc;  Rindx rdst;  Shamt shamt;  } SRA;
rlm@8:   struct { Rindx rsrc;  Rindx rdst;  Rindx rshamt; } SLLV;
rlm@8:   struct { Rindx rsrc;  Rindx rdst;  Rindx rshamt; } SRLV;
rlm@8:   struct { Rindx rsrc;  Rindx rdst;  Rindx rshamt; } SRAV;
rlm@8:   struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } ADDU;
rlm@8:   struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } SUBU;
rlm@8:   struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } AND;
rlm@8:   struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } OR;
rlm@8:   struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } XOR;
rlm@8:   struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } NOR;
rlm@8:   struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } SLT;
rlm@8:   struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } SLTU;
rlm@8: 
rlm@8:   struct { Target target;                          } J;
rlm@8:   struct { Target target;                          } JAL;
rlm@8:   struct { Rindx rsrc;                             } JR;
rlm@8:   struct { Rindx rsrc;  Rindx rdst;                } JALR;
rlm@8:   struct { Rindx rsrc1; Rindx rsrc2; Simm offset;  } BEQ;
rlm@8:   struct { Rindx rsrc1; Rindx rsrc2; Simm offset;  } BNE;
rlm@8:   struct { Rindx rsrc;  Simm offset;               } BLEZ;
rlm@8:   struct { Rindx rsrc;  Simm offset;               } BGTZ;
rlm@8:   struct { Rindx rsrc;  Simm offset;               } BLTZ;
rlm@8:   struct { Rindx rsrc;  Simm offset;               } BGEZ;
rlm@8: 
rlm@8:   struct { Rindx rdst;  CP0indx cop0src;           } MFC0;
rlm@8:   struct { Rindx rsrc;  CP0indx cop0dst;           } MTC0; 
rlm@8: 
rlm@8:   void                                               ILLEGAL;
rlm@8: 
rlm@8: }
rlm@8: Instr deriving(Eq);
rlm@8: 
rlm@8: //----------------------------------------------------------------------
rlm@8: // Pack and Unpack
rlm@8: //----------------------------------------------------------------------
rlm@8: 
rlm@8: Bit#(6) opFUNC  = 6'b000000;  Bit#(6) fcSLL   = 6'b000000;
rlm@8: Bit#(6) opRT    = 6'b000001;  Bit#(6) fcSRL   = 6'b000010;
rlm@8: Bit#(6) opRS    = 6'b010000;  Bit#(6) fcSRA   = 6'b000011;
rlm@8:                               Bit#(6) fcSLLV  = 6'b000100;
rlm@8: Bit#(6) opLW    = 6'b100011;  Bit#(6) fcSRLV  = 6'b000110;
rlm@8: Bit#(6) opSW    = 6'b101011;  Bit#(6) fcSRAV  = 6'b000111;
rlm@8:                               Bit#(6) fcADDU  = 6'b100001;
rlm@8: Bit#(6) opADDIU = 6'b001001;  Bit#(6) fcSUBU  = 6'b100011;
rlm@8: Bit#(6) opSLTI  = 6'b001010;  Bit#(6) fcAND   = 6'b100100;
rlm@8: Bit#(6) opSLTIU = 6'b001011;  Bit#(6) fcOR    = 6'b100101;
rlm@8: Bit#(6) opANDI  = 6'b001100;  Bit#(6) fcXOR   = 6'b100110;
rlm@8: Bit#(6) opORI   = 6'b001101;  Bit#(6) fcNOR   = 6'b100111;
rlm@8: Bit#(6) opXORI  = 6'b001110;  Bit#(6) fcSLT   = 6'b101010;
rlm@8: Bit#(6) opLUI   = 6'b001111;  Bit#(6) fcSLTU  = 6'b101011;
rlm@8: 
rlm@8: Bit#(6) opJ     = 6'b000010;
rlm@8: Bit#(6) opJAL   = 6'b000011;
rlm@8: Bit#(6) fcJR    = 6'b001000;
rlm@8: Bit#(6) fcJALR  = 6'b001001;
rlm@8: Bit#(6) opBEQ   = 6'b000100;
rlm@8: Bit#(6) opBNE   = 6'b000101;
rlm@8: Bit#(6) opBLEZ  = 6'b000110;
rlm@8: Bit#(6) opBGTZ  = 6'b000111;
rlm@8: Bit#(5) rtBLTZ  = 5'b00000;
rlm@8: Bit#(5) rtBGEZ  = 5'b00001;
rlm@8: 
rlm@8: Bit#(5) rsMFC0  = 5'b00000;
rlm@8: Bit#(5) rsMTC0  = 5'b00100;
rlm@8: 
rlm@8: instance Bits#(Instr,32);
rlm@8: 
rlm@8:   // Pack Function
rlm@8: 
rlm@8:   function Bit#(32) pack( Instr instr );
rlm@8: 
rlm@8:     case ( instr ) matches
rlm@8: 
rlm@8:       tagged LW    .it : return { opLW,    it.rbase, it.rdst,  it.offset };
rlm@8:       tagged SW    .it : return { opSW,    it.rbase, it.rsrc,  it.offset };
rlm@8: 
rlm@8:       tagged ADDIU .it : return { opADDIU, it.rsrc,  it.rdst,  it.imm                      }; 
rlm@8:       tagged SLTI  .it : return { opSLTI,  it.rsrc,  it.rdst,  it.imm                      }; 
rlm@8:       tagged SLTIU .it : return { opSLTIU, it.rsrc,  it.rdst,  it.imm                      }; 
rlm@8:       tagged ANDI  .it : return { opANDI,  it.rsrc,  it.rdst,  it.imm                      }; 
rlm@8:       tagged ORI   .it : return { opORI,   it.rsrc,  it.rdst,  it.imm                      }; 
rlm@8:       tagged XORI  .it : return { opXORI,  it.rsrc,  it.rdst,  it.imm                      }; 
rlm@8:       tagged LUI   .it : return { opLUI,   5'b0,     it.rdst,  it.imm                      };
rlm@8: 
rlm@8:       tagged SLL   .it : return { opFUNC,  5'b0,     it.rsrc,  it.rdst,   it.shamt, fcSLL  }; 
rlm@8:       tagged SRL   .it : return { opFUNC,  5'b0,     it.rsrc,  it.rdst,   it.shamt, fcSRL  }; 
rlm@8:       tagged SRA   .it : return { opFUNC,  5'b0,     it.rsrc,  it.rdst,   it.shamt, fcSRA  }; 
rlm@8: 
rlm@8:       tagged SLLV  .it : return { opFUNC,  it.rshamt, it.rsrc, it.rdst,   5'b0,     fcSLLV }; 
rlm@8:       tagged SRLV  .it : return { opFUNC,  it.rshamt, it.rsrc, it.rdst,   5'b0,     fcSRLV }; 
rlm@8:       tagged SRAV  .it : return { opFUNC,  it.rshamt, it.rsrc, it.rdst,   5'b0,     fcSRAV }; 
rlm@8: 
rlm@8:       tagged ADDU  .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcADDU }; 
rlm@8:       tagged SUBU  .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcSUBU }; 
rlm@8:       tagged AND   .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcAND  }; 
rlm@8:       tagged OR    .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcOR   }; 
rlm@8:       tagged XOR   .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcXOR  }; 
rlm@8:       tagged NOR   .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcNOR  }; 
rlm@8:       tagged SLT   .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcSLT  }; 
rlm@8:       tagged SLTU  .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcSLTU }; 
rlm@8: 
rlm@8:       tagged J     .it : return { opJ,     it.target                                       }; 
rlm@8:       tagged JAL   .it : return { opJAL,   it.target                                       }; 
rlm@8:       tagged JR    .it : return { opFUNC,  it.rsrc,  5'b0,     5'b0,      5'b0,     fcJR   };
rlm@8:       tagged JALR  .it : return { opFUNC,  it.rsrc,  5'b0,     it.rdst,   5'b0,     fcJALR };
rlm@8:       tagged BEQ   .it : return { opBEQ,   it.rsrc1, it.rsrc2, it.offset                   }; 
rlm@8:       tagged BNE   .it : return { opBNE,   it.rsrc1, it.rsrc2, it.offset                   }; 
rlm@8:       tagged BLEZ  .it : return { opBLEZ,  it.rsrc,  5'b0,     it.offset                   }; 
rlm@8:       tagged BGTZ  .it : return { opBGTZ,  it.rsrc,  5'b0,     it.offset                   }; 
rlm@8:       tagged BLTZ  .it : return { opRT,    it.rsrc,  rtBLTZ,   it.offset                   }; 
rlm@8:       tagged BGEZ  .it : return { opRT,    it.rsrc,  rtBGEZ,   it.offset                   }; 
rlm@8: 
rlm@8:       tagged MFC0  .it : return { opRS,    rsMFC0,   it.rdst,  it.cop0src, 11'b0           }; 
rlm@8:       tagged MTC0  .it : return { opRS,    rsMTC0,   it.rsrc,  it.cop0dst, 11'b0           };  
rlm@8: 
rlm@8:     endcase
rlm@8: 
rlm@8:   endfunction
rlm@8: 
rlm@8:   // Unpack Function
rlm@8: 
rlm@8:   function Instr unpack( Bit#(32) instrBits );
rlm@8: 
rlm@8:     let opcode = instrBits[ 31 : 26 ];
rlm@8:     let rs     = instrBits[ 25 : 21 ];
rlm@8:     let rt     = instrBits[ 20 : 16 ];
rlm@8:     let rd     = instrBits[ 15 : 11 ];
rlm@8:     let shamt  = instrBits[ 10 :  6 ];
rlm@8:     let funct  = instrBits[  5 :  0 ];
rlm@8:     let imm    = instrBits[ 15 :  0 ];
rlm@8:     let target = instrBits[ 25 :  0 ];
rlm@8: 
rlm@8:     case ( opcode )
rlm@8: 
rlm@8:       opLW        : return LW    { rbase:rs, rdst:rt,  offset:imm  };
rlm@8:       opSW        : return SW    { rbase:rs, rsrc:rt,  offset:imm  };
rlm@8:       opADDIU     : return ADDIU { rsrc:rs,  rdst:rt,  imm:imm     };
rlm@8:       opSLTI      : return SLTI  { rsrc:rs,  rdst:rt,  imm:imm     };
rlm@8:       opSLTIU     : return SLTIU { rsrc:rs,  rdst:rt,  imm:imm     };
rlm@8:       opANDI      : return ANDI  { rsrc:rs,  rdst:rt,  imm:imm     };
rlm@8:       opORI       : return ORI   { rsrc:rs,  rdst:rt,  imm:imm     };
rlm@8:       opXORI      : return XORI  { rsrc:rs,  rdst:rt,  imm:imm     };
rlm@8:       opLUI       : return LUI   {           rdst:rt,  imm:imm     };
rlm@8:       opJ         : return J     { target:target                   };
rlm@8:       opJAL       : return JAL   { target:target                   };
rlm@8:       opBEQ       : return BEQ   { rsrc1:rs, rsrc2:rt, offset:imm  };
rlm@8:       opBNE       : return BNE   { rsrc1:rs, rsrc2:rt, offset:imm  };
rlm@8:       opBLEZ      : return BLEZ  { rsrc:rs,  offset:imm            };
rlm@8:       opBGTZ      : return BGTZ  { rsrc:rs,  offset:imm            };
rlm@8: 
rlm@8:       opFUNC  : 
rlm@8:         case ( funct )
rlm@8:           fcSLL   : return SLL   { rsrc:rt,  rdst:rd,  shamt:shamt };
rlm@8:           fcSRL   : return SRL   { rsrc:rt,  rdst:rd,  shamt:shamt };
rlm@8:           fcSRA   : return SRA   { rsrc:rt,  rdst:rd,  shamt:shamt };
rlm@8:           fcSLLV  : return SLLV  { rsrc:rt,  rdst:rd,  rshamt:rs   };
rlm@8:           fcSRLV  : return SRLV  { rsrc:rt,  rdst:rd,  rshamt:rs   };
rlm@8:           fcSRAV  : return SRAV  { rsrc:rt,  rdst:rd,  rshamt:rs   };
rlm@8:           fcADDU  : return ADDU  { rsrc1:rs, rsrc2:rt, rdst:rd     };
rlm@8:           fcSUBU  : return SUBU  { rsrc1:rs, rsrc2:rt, rdst:rd     };
rlm@8:           fcAND   : return AND   { rsrc1:rs, rsrc2:rt, rdst:rd     };
rlm@8:           fcOR    : return OR    { rsrc1:rs, rsrc2:rt, rdst:rd     };
rlm@8:           fcXOR   : return XOR   { rsrc1:rs, rsrc2:rt, rdst:rd     };
rlm@8:           fcNOR   : return NOR   { rsrc1:rs, rsrc2:rt, rdst:rd     };
rlm@8:           fcSLT   : return SLT   { rsrc1:rs, rsrc2:rt, rdst:rd     }; 
rlm@8:           fcSLTU  : return SLTU  { rsrc1:rs, rsrc2:rt, rdst:rd     };
rlm@8:           fcJR    : return JR    { rsrc:rs                         };
rlm@8:           fcJALR  : return JALR  { rsrc:rs,  rdst:rd               };
rlm@8:           default : return ILLEGAL;
rlm@8:         endcase
rlm@8: 
rlm@8:       opRT : 
rlm@8:         case ( rt )
rlm@8:           rtBLTZ  : return BLTZ  { rsrc:rs,  offset:imm            };
rlm@8:           rtBGEZ  : return BGEZ  { rsrc:rs,  offset:imm            };
rlm@8:           default : return ILLEGAL;
rlm@8:         endcase
rlm@8: 
rlm@8:       opRS : 
rlm@8:         case ( rs )
rlm@8:           rsMFC0  : return MFC0  { rdst:rt,  cop0src:rd            };
rlm@8:           rsMTC0  : return MTC0  { rsrc:rt,  cop0dst:rd            };
rlm@8:           default : return ILLEGAL;
rlm@8:         endcase
rlm@8: 
rlm@8:       default : return ILLEGAL;
rlm@8:       
rlm@8:     endcase
rlm@8: 
rlm@8:   endfunction
rlm@8: 
rlm@8: endinstance
rlm@8: 
rlm@8: //----------------------------------------------------------------------
rlm@8: // Trace
rlm@8: //----------------------------------------------------------------------
rlm@8: 
rlm@8: instance Traceable#(Instr);
rlm@8: 
rlm@8:   function Action traceTiny( String loc, String ttag, Instr inst );
rlm@8:     case ( inst ) matches
rlm@8: 
rlm@8:       tagged LW    .it : $fdisplay(stderr,  " => %s:%s lw", loc,   ttag );
rlm@8:       tagged SW    .it : $fdisplay(stderr,  " => %s:%s sw", loc,   ttag );
rlm@8: 
rlm@8:       tagged ADDIU .it : $fdisplay(stderr,  " => %s:%s addi", loc, ttag );
rlm@8:       tagged SLTI  .it : $fdisplay(stderr,  " => %s:%s sli", loc,  ttag );
rlm@8:       tagged SLTIU .it : $fdisplay(stderr,  " => %s:%s sliu", loc, ttag );
rlm@8:       tagged ANDI  .it : $fdisplay(stderr,  " => %s:%s andi", loc, ttag );
rlm@8:       tagged ORI   .it : $fdisplay(stderr,  " => %s:%s ori", loc,  ttag );
rlm@8:       tagged XORI  .it : $fdisplay(stderr,  " => %s:%s xori", loc, ttag );
rlm@8:       tagged LUI   .it : $fdisplay(stderr,  " => %s:%s lui", loc,  ttag );
rlm@8:                                           
rlm@8:       tagged SLL   .it : $fdisplay(stderr,  " => %s:%s sll", loc,  ttag );
rlm@8:       tagged SRL   .it : $fdisplay(stderr,  " => %s:%s srl", loc,  ttag );
rlm@8:       tagged SRA   .it : $fdisplay(stderr,  " => %s:%s sra", loc,  ttag );
rlm@8:       tagged SLLV  .it : $fdisplay(stderr,  " => %s:%s sllv", loc, ttag );
rlm@8:       tagged SRLV  .it : $fdisplay(stderr,  " => %s:%s srlv", loc, ttag );
rlm@8:       tagged SRAV  .it : $fdisplay(stderr,  " => %s:%s srav", loc, ttag );
rlm@8:                                           
rlm@8:       tagged ADDU  .it : $fdisplay(stderr,  " => %s:%s addu", loc, ttag );
rlm@8:       tagged SUBU  .it : $fdisplay(stderr,  " => %s:%s subu", loc, ttag );
rlm@8:       tagged AND   .it : $fdisplay(stderr,  " => %s:%s and", loc,  ttag );
rlm@8:       tagged OR    .it : $fdisplay(stderr,  " => %s:%s or", loc,   ttag );
rlm@8:       tagged XOR   .it : $fdisplay(stderr,  " => %s:%s xor", loc,  ttag );
rlm@8:       tagged NOR   .it : $fdisplay(stderr,  " => %s:%s nor", loc,  ttag );
rlm@8:       tagged SLT   .it : $fdisplay(stderr,  " => %s:%s slt", loc,  ttag );
rlm@8:       tagged SLTU  .it : $fdisplay(stderr,  " => %s:%s sltu", loc, ttag );
rlm@8:                                           
rlm@8:       tagged J     .it : $fdisplay(stderr,  " => %s:%s j", loc,    ttag );
rlm@8:       tagged JAL   .it : $fdisplay(stderr,  " => %s:%s jal", loc,  ttag );
rlm@8:       tagged JR    .it : $fdisplay(stderr,  " => %s:%s jr", loc,   ttag );
rlm@8:       tagged JALR  .it : $fdisplay(stderr,  " => %s:%s jalr", loc, ttag );
rlm@8:       tagged BEQ   .it : $fdisplay(stderr,  " => %s:%s beq", loc,  ttag );
rlm@8:       tagged BNE   .it : $fdisplay(stderr,  " => %s:%s bne", loc,  ttag );
rlm@8:       tagged BLEZ  .it : $fdisplay(stderr,  " => %s:%s blez", loc, ttag );
rlm@8:       tagged BGTZ  .it : $fdisplay(stderr,  " => %s:%s bgtz", loc, ttag );
rlm@8:       tagged BLTZ  .it : $fdisplay(stderr,  " => %s:%s bltz", loc, ttag );
rlm@8:       tagged BGEZ  .it : $fdisplay(stderr,  " => %s:%s bgez", loc, ttag );
rlm@8:                                            
rlm@8:       tagged MFC0  .it : $fdisplay(stderr,  " => %s:%s mfc0", loc, ttag );
rlm@8:       tagged MTC0  .it : $fdisplay(stderr,  " => %s:%s mtc0", loc, ttag );
rlm@8: 
rlm@8:       tagged ILLEGAL   : $fdisplay(stderr,  " => %s:%s ill", loc,  ttag );
rlm@8: 
rlm@8:     endcase
rlm@8:   endfunction
rlm@8: 
rlm@8:   function Action traceFull( String loc, String ttag, Instr inst );
rlm@8:     case ( inst ) matches
rlm@8: 
rlm@8:       tagged LW    .it : $fdisplay(stderr,  " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase );
rlm@8:       tagged SW    .it : $fdisplay(stderr,  " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase );
rlm@8: 
rlm@8:       tagged ADDIU .it : $fdisplay(stderr,  " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
rlm@8:       tagged SLTI  .it : $fdisplay(stderr,  " => %s:%s slti r%0d, r%0d, 0x%x", loc,  ttag, it.rdst, it.rsrc, it.imm );
rlm@8:       tagged SLTIU .it : $fdisplay(stderr,  " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
rlm@8:       tagged ANDI  .it : $fdisplay(stderr,  " => %s:%s andi r%0d, r%0d, 0x%x", loc,  ttag, it.rdst, it.rsrc, it.imm );
rlm@8:       tagged ORI   .it : $fdisplay(stderr,  " => %s:%s ori r%0d, r%0d, 0x%x", loc,   ttag, it.rdst, it.rsrc, it.imm );
rlm@8:       tagged XORI  .it : $fdisplay(stderr,  " => %s:%s xori r%0d, r%0d, 0x%x", loc,  ttag, it.rdst, it.rsrc, it.imm );
rlm@8:       tagged LUI   .it : $fdisplay(stderr,  " => %s:%s lui r%0d, 0x%x", loc,         ttag, it.rdst, it.imm );
rlm@8:                                       
rlm@8:       tagged SLL   .it : $fdisplay(stderr,  " => %s:%s sll r%0d, r%0d, %0d", loc,   ttag, it.rdst, it.rsrc, it.shamt );
rlm@8:       tagged SRL   .it : $fdisplay(stderr,  " => %s:%s srl r%0d, r%0d, %0d", loc,   ttag, it.rdst, it.rsrc, it.shamt );
rlm@8:       tagged SRA   .it : $fdisplay(stderr,  " => %s:%s sra r%0d, r%0d, %0d", loc,   ttag, it.rdst, it.rsrc, it.shamt );
rlm@8:       tagged SLLV  .it : $fdisplay(stderr,  " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
rlm@8:       tagged SRLV  .it : $fdisplay(stderr,  " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
rlm@8:       tagged SRAV  .it : $fdisplay(stderr,  " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
rlm@8:                                       
rlm@8:       tagged ADDU  .it : $fdisplay(stderr,  " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
rlm@8:       tagged SUBU  .it : $fdisplay(stderr,  " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
rlm@8:       tagged AND   .it : $fdisplay(stderr,  " => %s:%s and r%0d, r%0d, r%0d", loc,  ttag, it.rdst, it.rsrc1, it.rsrc2 );
rlm@8:       tagged OR    .it : $fdisplay(stderr,  " => %s:%s or r%0d, r%0d, r%0d", loc,   ttag, it.rdst, it.rsrc1, it.rsrc2 );
rlm@8:       tagged XOR   .it : $fdisplay(stderr,  " => %s:%s xor r%0d, r%0d, r%0d", loc,  ttag, it.rdst, it.rsrc1, it.rsrc2 );
rlm@8:       tagged NOR   .it : $fdisplay(stderr,  " => %s:%s nor r%0d, r%0d, r%0d", loc,  ttag, it.rdst, it.rsrc1, it.rsrc2 );
rlm@8:       tagged SLT   .it : $fdisplay(stderr,  " => %s:%s slt r%0d, r%0d, r%0d", loc,  ttag, it.rdst, it.rsrc1, it.rsrc2 );
rlm@8:       tagged SLTU  .it : $fdisplay(stderr,  " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
rlm@8:                                       
rlm@8:       tagged J     .it : $fdisplay(stderr,  " => %s:%s j 0x%x", loc,    ttag, it.target );
rlm@8:       tagged JAL   .it : $fdisplay(stderr,  " => %s:%s jal 0x%x", loc,  ttag, it.target );
rlm@8:       tagged JR    .it : $fdisplay(stderr,  " => %s:%s jr r%0d", loc,   ttag, it.rsrc );
rlm@8:       tagged JALR  .it : $fdisplay(stderr,  " => %s:%s jalr r%0d", loc, ttag, it.rsrc );
rlm@8:       tagged BEQ   .it : $fdisplay(stderr,  " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset );
rlm@8:       tagged BNE   .it : $fdisplay(stderr,  " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset );
rlm@8:       tagged BLEZ  .it : $fdisplay(stderr,  " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
rlm@8:       tagged BGTZ  .it : $fdisplay(stderr,  " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
rlm@8:       tagged BLTZ  .it : $fdisplay(stderr,  " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
rlm@8:       tagged BGEZ  .it : $fdisplay(stderr,  " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
rlm@8:                                       
rlm@8:       tagged MFC0  .it : $fdisplay(stderr,  " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src );
rlm@8:       tagged MTC0  .it : $fdisplay(stderr,  " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst );
rlm@8: 
rlm@8:       tagged ILLEGAL   : $fdisplay(stderr,  " => %s:%s illegal instruction", loc, ttag );
rlm@8: 
rlm@8:     endcase
rlm@8:   endfunction
rlm@8: 
rlm@8: endinstance
rlm@8: