Mercurial > pygar
view modules/bluespec/Pygar/lab4/Core.bsv @ 76:8bd0e4d37ad2 pygar svn.77 tip
[svn r77] I don't know why my last change didn't go through grumble grumble....
author | rlm |
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date | Wed, 12 May 2010 08:58:23 -0400 |
parents | 74716e9a81cc |
children |
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1 // The MIT License3 // Copyright (c) 2009 Massachusetts Institute of Technology5 // Permission is hereby granted, free of charge, to any person obtaining a copy6 // of this software and associated documentation files (the "Software"), to deal7 // in the Software without restriction, including without limitation the rights8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell9 // copies of the Software, and to permit persons to whom the Software is10 // furnished to do so, subject to the following conditions:12 // The above copyright notice and this permission notice shall be included in13 // all copies or substantial portions of the Software.15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN21 // THE SOFTWARE.23 import Connectable::*;24 import GetPut::*;25 import ClientServer::*;27 //AWB includes28 `include "asim/provides/low_level_platform_interface.bsh"29 `include "asim/provides/soft_connections.bsh"30 `include "asim/provides/common_services.bsh"32 // Local includes33 `include "asim/provides/processor_library.bsh"34 `include "asim/provides/mem_arb.bsh"35 `include "asim/provides/instruction_cache.bsh"36 `include "asim/provides/data_cache.bsh"37 `include "asim/provides/processor.bsh"41 interface Core;43 // Interface from core to main memory44 interface Client#(MainMemReq,MainMemResp) mmem_client;46 endinterface48 module [CONNECTED_MODULE] mkCore( Core );50 // Instantiate the modules52 Proc proc <- mkProc();53 ICache#(InstReq,InstResp) icache <- mkInstCache();54 DCache#(DataReq,DataResp) dcache <- mkDataCache();55 MemArb marb <- mkMemArb();57 // Internal connections59 mkConnection( proc.statsEn_get, icache.statsEn_put );60 mkConnection( proc.statsEn_get, dcache.statsEn_put );61 mkConnection( proc.imem_client, icache.proc_server );62 mkConnection( proc.dmem_client, dcache.proc_server );63 mkConnection( icache.mmem_client, marb.cache0_server );64 mkConnection( dcache.mmem_client, marb.cache1_server );66 // Methods68 interface mmem_client = marb.mmem_client;70 endmodule