Mercurial > pygar
view modules/bluespec/Pygar/core/mixer.bsv~ @ 71:86360c5ae9f2 pygar svn.72
[svn r72] added config for htg
author | punk |
---|---|
date | Wed, 12 May 2010 00:21:40 -0400 |
parents | 2c8166d205d5 |
children |
line wrap: on
line source
1 // The MIT License3 // Copyright (c) 2009 Massachusetts Institute of Technology5 // Permission is hereby granted, free of charge, to any person obtaining a copy6 // of this software and associated documentation files (the "Software"), to deal7 // in the Software without restriction, including without limitation the rights8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell9 // copies of the Software, and to permit persons to whom the Software is10 // furnished to do so, subject to the following conditions:12 // The above copyright notice and this permission notice shall be included in13 // all copies or substantial portions of the Software.15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN21 // THE SOFTWARE.23 import Connectable::*;24 import GetPut::*;25 import ClientServer::*;26 import Processor::*;27 import MemArb::*;28 import MemTypes::*;30 //AWB includes31 `include "asim/provides/low_level_platform_interface.bsh"32 `include "asim/provides/soft_connections.bsh"33 `include "asim/provides/common_services.bsh"35 // Local includes36 `include "asim/provides/processor_library.bsh"37 `include "asim/provides/processor.bsh"38 `include "asim/provides/audio_pipe_types.bsh"40 interface Core;42 // Interface from core to main memory43 interface Client#(MainMemReq,MainMemResp) mmem_client;45 interface Get#(AudioProcessorUnit) sampleOutput;47 endinterface49 module [CONNECTED_MODULE] mkCore( Core );51 // Instantiate the modules53 Proc proc <- mkProc();54 ICache#(InstReq,InstResp) icache <- mkInstCache();55 DCache#(DataReq,DataResp) dcache <- mkDataCache();56 MemArb marb <- mkMemArb();58 // Internal connections60 interface sampleOutput = proc.sampleOutput;62 endmodule