view modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv @ 69:5c963ab14143 pygar svn.70

[svn r70] added an attempt at multi-fileing
author punk
date Wed, 12 May 2010 00:07:40 -0400
parents 1d5cbb5343d2
children
line wrap: on
line source
1 // The MIT License
3 // Copyright (c) 2009 Massachusetts Institute of Technology
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
23 import Connectable::*;
24 import GetPut::*;
25 import ClientServer::*;
26 import RegFile::*;
27 import FIFO::*;
28 import FIFOF::*;
29 import RWire::*;
30 import Trace::*;
32 // Local includes
33 `include "asim/provides/low_level_platform_interface.bsh"
34 `include "asim/provides/soft_connections.bsh"
35 `include "asim/provides/processor_library.bsh"
36 `include "asim/provides/fpga_components.bsh"
37 `include "asim/provides/common_services.bsh"
39 interface ICache#( type req_t, type resp_t );
41 // Interface from processor to cache
42 interface Server#(req_t,resp_t) proc_server;
44 // Interface from cache to main memory
45 interface Client#(MainMemReq,MainMemResp) mmem_client;
47 // Interface for enabling/disabling statistics
48 interface Put#(Bool) statsEn_put;
50 endinterface
52 //----------------------------------------------------------------------
53 // Cache Types
54 //----------------------------------------------------------------------
56 typedef 10 CacheLineIndexSz;
57 typedef 20 CacheLineTagSz;
58 typedef 32 CacheLineSz;
60 typedef Bit#(CacheLineIndexSz) CacheLineIndex;
61 typedef Bit#(CacheLineTagSz) CacheLineTag;
62 typedef Bit#(CacheLineSz) CacheLine;
64 typedef enum
65 {
66 Init,
67 Access,
68 Evict,
69 RefillReq,
70 RefillResp
71 }
72 CacheStage
73 deriving (Eq,Bits);
75 //----------------------------------------------------------------------
76 // Helper functions
77 //----------------------------------------------------------------------
79 function Bit#(AddrSz) getAddr( InstReq req );
81 Bit#(AddrSz) addr = ?;
82 case ( req ) matches
83 tagged LoadReq .ld : addr = ld.addr;
84 tagged StoreReq .st : addr = st.addr;
85 endcase
87 return addr;
89 endfunction
91 function CacheLineIndex getCacheLineIndex( InstReq req );
92 Bit#(AddrSz) addr = getAddr(req);
93 Bit#(CacheLineIndexSz) index = truncate( addr >> 2 );
94 return index;
95 endfunction
97 function CacheLineTag getCacheLineTag( InstReq req );
98 Bit#(AddrSz) addr = getAddr(req);
99 Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 );
100 return tag;
101 endfunction
103 function Bit#(AddrSz) getCacheLineAddr( InstReq req );
104 Bit#(AddrSz) addr = getAddr(req);
105 return ((addr >> 2) << 2);
106 endfunction
108 //----------------------------------------------------------------------
109 // Main module
110 //----------------------------------------------------------------------
112 (* doc = "synthesis attribute ram_style mkInstCache distributed;" *)
113 (* synthesize *)
114 module mkInstCache( ICache#(InstReq,InstResp) );
116 //-----------------------------------------------------------
117 // State
119 Reg#(CacheStage) stage <- mkReg(Init);
121 LUTRAM#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkLUTRAMU_RegFile();
122 LUTRAM#(CacheLineIndex,CacheLine) cacheDataRam <- mkLUTRAMU_RegFile();
124 FIFO#(InstReq) reqQ <- mkFIFO();
125 FIFOF#(InstResp) respQ <- mkBFIFOF1();
127 FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1();
128 FIFO#(MainMemResp) mainMemRespQ <- mkFIFO();
130 Reg#(CacheLineIndex) initCounter <- mkReg(1);
132 // Statistics state
134 Reg#(Bool) statsEn <- mkReg(False);
136 //rlm:
137 //STAT num_accesses <- mkStatCounter(`STATS_INST_CACHE_NUM_ACCESSES);
138 //STAT num_misses <- mkStatCounter(`STATS_INST_CACHE_NUM_MISSES);
139 //STAT num_evictions <- mkStatCounter(`STATS_INST_CACHE_NUM_EVICTIONS);
141 //-----------------------------------------------------------
142 // Name some wires
144 let req = reqQ.first();
145 let reqIndex = getCacheLineIndex(req);
146 let reqTag = getCacheLineTag(req);
147 let reqCacheLineAddr = getCacheLineAddr(req);
148 let refill = mainMemRespQ.first();
150 //-----------------------------------------------------------
151 // Initialize
153 rule init ( stage == Init );
154 traceTiny("mkInstCacheBlocking", "stage","i");
155 initCounter <= initCounter + 1;
156 cacheTagRam.upd(initCounter,Invalid);
157 if ( initCounter == 0 )
158 stage <= Access;
159 endrule
161 //-----------------------------------------------------------
162 // Cache access rule
164 rule access ( (stage == Access) && respQ.notFull() );
166 // Statistics
167 //rlm:
168 // if ( statsEn )
169 // num_accesses.incr();
171 // Check tag and valid bit to see if this is a hit or a miss
173 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);
175 // Handle cache hits ...
177 if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) )
178 begin
179 traceTiny("mkInstCacheBlocking", "hitMiss","h");
180 reqQ.deq();
182 case ( req ) matches
184 tagged LoadReq .ld :
185 respQ.enq( LoadResp { tag : ld.tag, data : cacheDataRam.sub(reqIndex) } );
187 tagged StoreReq .st :
188 $display( " RTL-ERROR : %m : Stores are not allowed on the inst port!" );
190 endcase
192 end
194 // Handle cache misses - since lines in instruction cache are
195 // never dirty we can always immediately issue a refill request
197 else
198 begin
199 traceTiny("mkInstCacheBlocking", "hitMiss","m");
200 //rlm:
201 //if ( statsEn )
202 //num_misses.incr();
203 //if ( statsEn )
204 //if ( isJust(cacheLineTag) )
205 //num_evictions.incr();
207 MainMemReq rfReq
208 = LoadReq { tag : 0,
209 addr : reqCacheLineAddr };
211 mainMemReqQ.enq(rfReq);
212 stage <= RefillResp;
213 end
215 endrule
217 //-----------------------------------------------------------
218 // Refill response rule
220 rule refillResp ( stage == RefillResp );
221 traceTiny("mkInstCacheBlocking", "stage","R");
222 traceTiny("mkInstCacheBlocking", "refill",refill);
224 // Write the new data into the cache and update the tag
226 mainMemRespQ.deq();
227 case ( mainMemRespQ.first() ) matches
229 tagged LoadResp .ld :
230 begin
231 cacheTagRam.upd(reqIndex,Valid(reqTag));
232 cacheDataRam.upd(reqIndex,ld.data);
233 end
235 tagged StoreResp .st :
236 noAction;
238 endcase
240 stage <= Access;
241 endrule
243 //-----------------------------------------------------------
244 // Methods
246 interface Client mmem_client;
247 interface Get request = fifoToGet(mainMemReqQ);
248 interface Put response = fifoToPut(mainMemRespQ);
249 endinterface
251 interface Server proc_server;
252 interface Put request = tracePut("mkInstCacheBlocking", "reqTiny",fifoToPut(reqQ));
253 interface Get response = traceGet("mkInstCacheBlocking", "respTiny",fifofToGet(respQ));
254 endinterface
256 interface Put statsEn_put = regToPut(statsEn);
258 endmodule