// The MIT License

 

 // Copyright (c) 2009 Massachusetts Institute of Technology

 

 // Permission is hereby granted, free of charge, to any person obtaining a copy

 // of this software and associated documentation files (the "Software"), to deal

 // in the Software without restriction, including without limitation the rights

 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 // copies of the Software, and to permit persons to whom the Software is

 // furnished to do so, subject to the following conditions:

 

 // The above copyright notice and this permission notice shall be included in

 // all copies or substantial portions of the Software.

 

 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 // THE SOFTWARE.

 

 

 import Connectable::*;

 import GetPut::*;

 import ClientServer::*;

 import RegFile::*;

 

 import FIFO::*;

 import FIFOF::*;

 import SFIFO::*;

 import RWire::*;

 

 import Trace::*;

 import BFIFO::*;

 import MemTypes::*;

 import ProcTypes::*;

 import BRegFile::*;

 import BranchPred::*;

 

 //AWB includes

 `include "asim/provides/low_level_platform_interface.bsh"

 `include "asim/provides/soft_connections.bsh"

 `include "asim/provides/common_services.bsh"

 

 // Local includes

 //`include "asim/provides/processor_library.bsh" (included above directly)

 

 `include "asim/provides/common_services.bsh"

 `include "asim/provides/processor_library.bsh"

 

 // Local includes. Look for the correspondingly named .awb files

 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/

 // to find the actual Bluespec files which are used to generate

 // these includes.  These files are specific to this audio processing

 // pipeline

 

 `include "asim/provides/audio_pipe_types.bsh"

 `include "asim/provides/path_types.bsh"

 

 //interface CPUToHost;

 //  method Bit#(32) cpuToHost(int req);

 //endinterface

 

 interface Proc;

 

   // Interface from processor to caches

   interface Client#(DataReq,DataResp) dmem_client;

   interface Client#(InstReq,InstResp) imem_client;

 

   // Interface for enabling/disabling statistics on the rest of the core

   interface Get#(Bool) statsEn_get;

 

   // Interface to host

   interface Get#(Bit#(32)) pcCount;

 

   // Interface to Audio Pipeline

   interface Get#(AudioStream) sampleOutput;

   interface Put#(AudioStream) sampleInput;

 	

 endinterface

 

 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);

 

 //-----------------------------------------------------------

 // Helper functions

 //-----------------------------------------------------------

 

 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );

    return zeroExtend( pack( signedLT(val1,val2) ) );

 endfunction

 

 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );

    return zeroExtend( pack( val1 < val2 ) );

 endfunction

 

 function Bit#(32) rshft( Bit#(32) val );

    return zeroExtend(val[4:0]);

 endfunction

 

 

 //-----------------------------------------------------------

 // Find funct for wbQ

 //-----------------------------------------------------------

 function Bool findwbf(Rindx fVal, WBResult cmpVal);

   case (cmpVal) matches   

      tagged WB_ALU  {data:.res, dest:.rd} :

 	return (fVal == rd);

      tagged WB_Load .rd  :

 	return (fVal == rd);

      tagged WB_Store .st :

 	return False;

      tagged WB_Host .x   :

 	return False;

   endcase

 endfunction

 

      

 //-----------------------------------------------------------

 // Stall funct for wbQ

 //-----------------------------------------------------------

 function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);

    case (inst) matches

       	 // -- Memory Ops ------------------------------------------------      

       tagged LW .it :

 	 return f.find(it.rbase);

       tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :

 	 return (f.find(addr) ||  f.find2(dreg));

 

 	 // -- Simple Ops ------------------------------------------------      

       tagged ADDIU .it : return f.find(it.rsrc);

       tagged SLTI  .it : return f.find(it.rsrc);

       tagged SLTIU .it : return f.find(it.rsrc);

       tagged ANDI  .it : return f.find(it.rsrc);

       tagged ORI   .it : return f.find(it.rsrc);

       tagged XORI  .it : return f.find(it.rsrc);

       

       tagged LUI   .it : return f.find(it.rdst);  //this rds/wrs itself

       tagged SLL   .it : return f.find(it.rsrc);

       tagged SRL   .it : return f.find(it.rsrc);

       tagged SRA   .it : return f.find(it.rsrc);

       tagged SLLV  .it : return (f.find(it.rsrc) || f.find(it.rshamt));

       tagged SRLV  .it : return (f.find(it.rsrc) || f.find(it.rshamt));

       tagged SRAV  .it : return (f.find(it.rsrc) || f.find(it.rshamt));

       tagged ADDU  .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

       tagged SUBU  .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

       tagged AND   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

       tagged OR    .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

       tagged XOR   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

       tagged NOR   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

       tagged SLT   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

       tagged SLTU  .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

    

 

       // -- Branches --------------------------------------------------

     

       tagged BLEZ  .it : return (f.find(it.rsrc));

       tagged BGTZ  .it : return (f.find(it.rsrc));

       tagged BLTZ  .it : return (f.find(it.rsrc));

       tagged BGEZ  .it : return (f.find(it.rsrc));

       tagged BEQ   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

       tagged BNE   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

       

       // -- Jumps -----------------------------------------------------

       

       tagged J     .it : return False;

       tagged JR    .it : return f.find(it.rsrc);

       tagged JALR  .it : return f.find(it.rsrc);

       tagged JAL   .it : return False;

       

       // -- Cop0 ------------------------------------------------------

       

       tagged MTC0  .it : return f.find(it.rsrc);      

       tagged MFC0  .it : return False; 

 

       // -- Illegal ---------------------------------------------------

 

       default : return False;

 

     endcase

 endfunction

 

 

 //-----------------------------------------------------------

 // Reference processor

 //-----------------------------------------------------------

 

 

 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)

 //(* synthesize *)

 

 module mkProc( Proc );

 

    //-----------------------------------------------------------

    // State

 

    // Standard processor state

    

    Reg#(Addr)  pc    <- mkReg(32'h00001000);

    Reg#(Epoch) epoch <- mkReg(0);

    Reg#(Stage) stage <- mkReg(PCgen);

    BRegFile      rf  <- mkBRegFile;

 

    // Branch Prediction

    BranchPred               bp <- mkBranchPred();

    FIFO#(PCStat)        execpc <- mkLFIFO();

    

    // Pipelines

    FIFO#(PCStat)           pcQ <-mkSizedFIFO(3);

    SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);

 

    // NEED TO ADD CAPABILITY FOR RESET (should be able to just say if I get valid in and these are flagged, clear them.

    Reg#(Bit#(32)) cp0_tohost   <- mkReg(0);

    Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);

    Reg#(Bool)     cp0_statsEn  <- mkReg(False);

    Reg#(Bool)     cp0_audioEOF <- mkReg(False);  // Register to let code that EOF is reached

    Reg#(Bool)     cp0_progComp <- mkReg(False);  // Register to let processor know that the program is complete (as this terminates)

  

    Reg#(Bool)     code_bypass  <- mkReg(True);   // Register to enable passing invalid packets once all valid ones are passed OUT 

                                                  // (this becomes false at first valid packet) 

     

    // Memory request/response state

    

    FIFO#(InstReq)  instReqQ    <- mkBFIFO1();

    FIFO#(InstResp) instRespQ   <- mkFIFO();

 

    FIFO#(DataReq)  dataReqQ    <- mkBFIFO1();

    FIFO#(DataResp) dataRespQ   <- mkFIFO();

 

    // Audio I/O

    FIFO#(AudioStream) inAudioFifo  <- mkSizedFIFO(512);

    FIFO#(AudioStream) outAudioFifo <- mkFIFO;

    Reg#(VoiceId)      channel      <-mkReg(0);  // Set based on the reading the incoming data.  Not entirely sure I like this.  What if the program generates samples?

 

    // Statistics state (2010)

    //   Reg#(Stat) num_cycles <- mkReg(0);

    //   Reg#(Stat) num_inst <- mkReg(0);

 

    //Or:

    // Statistics state

   

    //rlm: removing these to avoid their broken stupidness.

    //STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);

    //STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);

 

    //-----------------------------------------------------------

    // Internal Functions

 

    function Bool stallMTCO_MFCO(Instr inst);

       case(inst) matches

 	 tagged MTC0 .it : 

 	    begin

 	       case (it.cop0dst)

 		  5'd26 : return cp0_progComp;  // If true, processor service sendEnd which clears it.

 	       endcase

 	    end

       endcase					

    endfunction

    

    //-----------------------------------------------------------

    // Rules

 

    (* descending_urgency = "exec, pcgen" *)

    rule pcgen; //( stage == PCgen );

       let pc_plus4 = pc + 4;

 

       traceTiny("mkProc", "pc",pc);

       traceTiny("mkProc", "pcgen","P");

       instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );

       

       let next_pc = bp.get(pc);

       if (next_pc matches tagged Valid .npc) 

 	begin

 	   pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});

 	   pc <= npc;

 	end

      else

 	 begin

 	   pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});

 	   pc <= pc_plus4;

 	 end

       

    endrule

 

    rule discard (instRespQ.first() matches tagged LoadResp .ld

 					      &&& ld.tag != epoch);

       traceTiny("mkProc", "stage", "D");

       instRespQ.deq();

    endrule

 

    (* conflict_free = "exec, writeback" *)		      

    rule exec (instRespQ.first() matches tagged LoadResp.ld

 	      &&& (ld.tag == epoch)

 	      &&& unpack(ld.data) matches .inst

               &&& !stall(inst, wbQ)

 	      &&& !stallMTCO_MFCO(inst));

 

       // Some abbreviations

       let sext = signExtend;

       let zext = zeroExtend;

       let sra  = signedShiftRight;

       

       // Get the instruction

       

       instRespQ.deq();

       Instr inst 

       = case ( instRespQ.first() ) matches

 	   tagged LoadResp  .ld : return unpack(ld.data);

 	   tagged StoreResp .st : return ?;

 	endcase;

 

       // Get the PC info

       let instrpc = pcQ.first().qpc;

       let pc_plus4 = instrpc + 4;

       

       Bool branchTaken = False;

       Addr newPC = pc_plus4;

 

       // Tracing

       traceTiny("mkProc", "exec","X");

       traceTiny("mkProc", "exInstTiny",inst);

       traceFull("mkProc", "exInstFull",inst);

 

 //      $display("PROCESSOR: Exec Fires");

       case ( inst ) matches

 

 	 // -- Memory Ops ------------------------------------------------      

 

 	 tagged LW .it : 

 	    begin

 	       let val_rbase <- rf.rd1(it.rbase);

                Addr addr = val_rbase + sext(it.offset);

                dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );

                wbQ.enq(tagged WB_Load it.rdst);

 	    end

 

 	 tagged SW .it : 

 	    begin

 	       let val_rbase <- rf.rd1(it.rbase);

 	       let val_rsrc2 <- rf.rd2(it.rsrc);

                Addr addr = val_rbase + sext(it.offset);

                dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:val_rsrc2 } );

                wbQ.enq(tagged WB_Store);

 	    end

 

 	 // -- Simple Ops ------------------------------------------------      

 

 	 tagged ADDIU .it : 

 	    begin

 	       let val_rsrc1 <- rf.rd1(it.rsrc); 

 	       Bit#(32) result = val_rsrc1 + sext(it.imm);

 	       wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});

 	    end

 	 tagged SLTI  .it : 

 	    begin

 	       let val_rsrc1 <- rf.rd1(it.rsrc); 

 	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( val_rsrc1, sext(it.imm) )});

 	    end

 	 tagged SLTIU .it : 

 	    begin

 	       let val_rsrc1 <- rf.rd1(it.rsrc); 

 	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( val_rsrc1, sext(it.imm) ) });

 	    end

 	 tagged ANDI  .it : 

 	    begin

 	       let val_rsrc1 <- rf.rd1(it.rsrc); 

 	       Bit#(32) zext_it_imm = zext(it.imm);

 	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(val_rsrc1 & zext_it_imm)} );

 	    end

 	 tagged ORI   .it : 

 	    begin

 	       let val_rsrc1 <- rf.rd1(it.rsrc); 

 	       Bit#(32) zext_it_imm = zext(it.imm);

 	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(val_rsrc1 | zext_it_imm)} );

 	    end

 	 tagged XORI  .it : 

 	    begin

 	       let val_rsrc1 <- rf.rd1(it.rsrc); 

 	       Bit#(32) zext_it_imm = zext(it.imm);

 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 ^ zext_it_imm )});

 	    end

 	 tagged LUI   .it : 

 	    begin

 	       Bit#(32) zext_it_imm = zext(it.imm);

 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });

 	    end

 	 

 	 tagged SLL   .it : 

 	    begin

 	       let val_rsrc1 <- rf.rd1(it.rsrc); 

 	       Bit#(32) zext_it_shamt = zext(it.shamt);

 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 << zext_it_shamt )} );

 	    end

 	 tagged SRL   .it : 

 	    begin

 	       let val_rsrc1 <- rf.rd1(it.rsrc); 

 	       Bit#(32) zext_it_shamt = zext(it.shamt);

 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 >> zext_it_shamt )});

 	    end

 	 tagged SRA   .it : 

 	    begin

 	       let val_rsrc1 <- rf.rd1(it.rsrc); 

 	       Bit#(32) zext_it_shamt = zext(it.shamt);

 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( val_rsrc1, zext_it_shamt )});

 	    end

 	 tagged SLLV  .it : 

 	    begin

 	       let val_rsrc1 <- rf.rd1(it.rsrc);

 	       let val_rshamt <- rf.rd2(it.rshamt); 

 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 << rshft(val_rshamt) )});

 	    end	       

 	 tagged SRLV  .it : 

 	    begin

 	       let val_rsrc1 <- rf.rd1(it.rsrc); 

 	       let val_rshamt <- rf.rd2(it.rshamt); 

 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 >> rshft(val_rshamt) )} );

 	    end	       

 	 tagged SRAV  .it : 

 	    begin

 	       let val_rsrc1 <- rf.rd1(it.rsrc); 

 	       let val_rshamt <- rf.rd2(it.rshamt); 

 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( val_rsrc1, rshft(val_rshamt) ) });

 	    end	       

 	 tagged ADDU  .it : 

 	    begin

 	       let val_rsrc11 <- rf.rd1(it.rsrc1); 

 	       let val_rsrc22 <- rf.rd2(it.rsrc2); 

 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 + val_rsrc22 )} );

 	    end

 	 tagged SUBU  .it : 

 	    begin

 	       let val_rsrc11 <- rf.rd1(it.rsrc1); 

 	       let val_rsrc22 <- rf.rd2(it.rsrc2); 

 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 - val_rsrc22 )} );

 	    end

 	 tagged AND   .it : 

 	    begin

 	       let val_rsrc11 <- rf.rd1(it.rsrc1); 

 	       let val_rsrc22 <- rf.rd2(it.rsrc2); 

 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 & val_rsrc22 )} );

 	    end

 	 tagged OR    .it : 

 	    begin

 	       let val_rsrc11 <- rf.rd1(it.rsrc1); 

 	       let val_rsrc22 <- rf.rd2(it.rsrc2); 

 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 | val_rsrc22 )} );

 	    end

 	 tagged XOR   .it : 

 	    begin

 	       let val_rsrc11 <- rf.rd1(it.rsrc1); 

 	       let val_rsrc22 <- rf.rd2(it.rsrc2); 

 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 ^ val_rsrc22 )} );

 	    end

 	 tagged NOR   .it : 

 	    begin

 	       let val_rsrc11 <- rf.rd1(it.rsrc1); 

 	       let val_rsrc22 <- rf.rd2(it.rsrc2); 

 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(val_rsrc11 | val_rsrc22) )} );

 	    end

 	 tagged SLT   .it : 

 	    begin

 	       let val_rsrc11 <- rf.rd1(it.rsrc1); 

 	       let val_rsrc22 <- rf.rd2(it.rsrc2); 

 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( val_rsrc11, val_rsrc22 ) });

 	    end

 	 tagged SLTU  .it : 

 	    begin

 	       let val_rsrc11 <- rf.rd1(it.rsrc1); 

 	       let val_rsrc22 <- rf.rd2(it.rsrc2); 

 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( val_rsrc11, val_rsrc22 ) });

 	    end

 

 	 // -- Branches --------------------------------------------------

 

 	 tagged BLEZ  .it : 

 	    begin

 	       let val_rsrc1 <- rf.rd1(it.rsrc); 

 	         if ( signedLE( val_rsrc1, 0 ) )

 	       	 begin

 		  newPC = pc_plus4 + (sext(it.offset) << 2);

 		  branchTaken = True;

 	       	 end

 	    end

 

 	 tagged BGTZ  .it : 

 	    begin

 	       let val_rsrc1 <- rf.rd1(it.rsrc); 

                if ( signedGT( val_rsrc1, 0 ) ) 

                begin 

 		  newPC = pc_plus4 + (sext(it.offset) << 2);

 		  branchTaken = True;

 	       end

 	    end

 

 	 tagged BLTZ  .it : 

 	    begin

 	       let val_rsrc1 <- rf.rd1(it.rsrc); 

                if ( signedLT( val_rsrc1, 0 ) )

                begin 

 		  newPC = pc_plus4 + (sext(it.offset) << 2);

 		  branchTaken = True;

 	       end

 	    end

 		  

 	 tagged BGEZ  .it :

 	    begin

 	       let val_rsrc1 <- rf.rd1(it.rsrc); 

                  if ( signedGE( val_rsrc1, 0 ) )

                	 begin 

 		        newPC = pc_plus4 + (sext(it.offset) << 2);		  

 		  	branchTaken = True;

 	         end

 	    end

 

       tagged BEQ   .it : 

         begin

 	  let val_rsrc11 <- rf.rd1(it.rsrc1); 

 	  let val_rsrc22 <- rf.rd2(it.rsrc2); 

           if ( val_rsrc11 == val_rsrc22 )

           begin 

 	     newPC = pc_plus4 + (sext(it.offset) << 2);

 	     branchTaken = True;

 	  end

 	end

 

       tagged BNE   .it : 

         begin

 	  let val_rsrc11 <- rf.rd1(it.rsrc1); 

 	  let val_rsrc22 <- rf.rd2(it.rsrc2); 

           if ( val_rsrc11 != val_rsrc22 )

           begin 

 	     newPC = pc_plus4 + (sext(it.offset) << 2);

 	     branchTaken = True;

 	  end

 	end

 

       // -- Jumps -----------------------------------------------------

       

       tagged J     .it : 

         begin

 	   newPC = { pc_plus4[31:28], it.target, 2'b0 };

 	   branchTaken = True;

 	end

       

       tagged JR    .it : 

         begin

 	   let val_rsrc1 <- rf.rd1(it.rsrc); 

 	   newPC = val_rsrc1;

 	   branchTaken = True;

 	end

 

       tagged JAL   .it : 

        begin

           wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });

           newPC = { pc_plus4[31:28], it.target, 2'b0 };		  

 	  branchTaken = True;

        end

 

       tagged JALR  .it : 

        begin

 	  let val_rsrc1 <- rf.rd1(it.rsrc); 

           wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });

           newPC = val_rsrc1;

 	  branchTaken = True;

        end

 

       // -- Cop0 ------------------------------------------------------

       

       tagged MTC0  .it : //Recieve things from host computer

 	 begin

  	  let val_rsrc1 <- rf.rd1(it.rsrc); 

 //	    $display( " PROCESSOR MTC0 call\n");

             case ( it.cop0dst )

 	       5'd10 : cp0_statsEn <= unpack(truncate(val_rsrc1));

 	       5'd21 : cp0_tohost  <= truncate(val_rsrc1);

 	       5'd26 : cp0_progComp <= unpack(truncate(val_rsrc1)); //states audio program completed and termination okay

  	       5'd27 : outAudioFifo.enq(AudioStream {voice: channel, data: tagged Valid

 									   tagged Sample unpack(truncate(val_rsrc1)) });  //Bit size is 16 not 32

 	       default :

 	       $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );

 	    endcase

 	    wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.

 	 end

 

 //this is host stuff?

       tagged MFC0  .it :  //Things out

 	 begin

             case ( it.cop0src )

 	    // not actually an ALU instruction but don't have the format otherwise

                5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });

                5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });

                5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost   });

 	       5'd25 : begin

 //			  $display( "**** EOF Requested\n ");  //Should never run if inAudioFifo.first not valid

 			  let stream = inAudioFifo.first();

 			  if (stream.data matches tagged Valid .sample)

 			    begin

 			       case (sample) matches

 				  tagged EndOfFile :

 				     begin

 					$display("PROCESSOR sent toC EOF");

 					wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(True)) });  // Reading clears bit

 					inAudioFifo.deq;

 			              end

 				   tagged Sample .audio:

 				      wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(False)) });  // Reading clears bit

 			       endcase

 			       code_bypass <= False;

 			    end

 			  else $display("PROCESSOR code trying to read Invalid Audio Stream");

 		       end

 	       5'd28 : begin

 			  $display( "***** Reqesting Sample");

 			  let stream = inAudioFifo.first();        // is this going to cause perf. delay?

 			  if (stream.data matches tagged Valid .sample)

 			    begin			  

 			       if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF  

 	     			 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) });  // do I need pack?

 			       else $display ( "Audio File EOF Reached.  Invalid sample request.");

 			       inAudioFifo.deq();

 			    end

 			  else $display("PROCESSOR code trying to read Invalid Audio Stream");

 		       end

               default : 

                 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );

             endcase

 	end

 

       // -- Illegal ---------------------------------------------------

 

       default : 

         $display( " RTL-ERROR : %m : Illegal instruction !" );

 

     endcase

 

 //evaluate branch prediction

      Addr ppc = pcQ.first().qnxtpc; //predicted branch

      if (ppc != newPC) //prediction wrong

        begin

 	  epoch <= pcQ.first().qepoch + 1;

 	  bp.upd(instrpc, newPC); //update branch predictor

 	  pcQ.clear();

 	  pc <= newPC;

        end

      else

 	pcQ.deq();

    //rlm: removing

    // if ( cp0_statsEn )

    //   num_inst.incr();

 

   endrule

 

   rule writeback; // ( stage == Writeback );

      traceTiny("mkProc", "writeback","W");

      

 

     // get what to do off the writeback queue

      wbQ.deq();

      case (wbQ.first()) matches

 	tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);

 	tagged WB_Load .regWr : 

 	   begin

 	      dataRespQ.deq();

 	      if (dataRespQ.first() matches tagged LoadResp .ld)

 		rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue?  Duplicate?

 	   end

 	tagged WB_Store : dataRespQ.deq();

 	tagged WB_Host .dat : noAction;

      endcase

            

   endrule

 

 //rlm remove

  // rule inc_num_cycles;

  //   if ( cp0_statsEn )

  //     num_cycles.incr();

  // endrule

 

   rule bypass (code_bypass &&& 

 	      !cp0_progComp &&&   //never fires at the same time as sendEnd where it is enabled

               inAudioFifo.first().data matches tagged Invalid) ;

     outAudioFifo.enq(inAudioFifo.first());

     inAudioFifo.deq;

   endrule

 

 /*

   rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile);

      $display (" PROCESSOR End Audio Flag Set ");

      cp0_audioEOF <= True;

      inAudioFifo.deq;

   endrule

 */

   (* descending_urgency = "sendProcEnd, exec" *)

   rule sendProcEnd (cp0_progComp);

      $display (" PROCESSOR Says Program Complete ");

      outAudioFifo.enq(AudioStream {voice: channel, data: tagged Valid tagged EndOfFile });  //  Only send one

      cp0_progComp <= False;               //  And functions to reset

      code_bypass <= True;                 //  Enable Bypass so that invalids get thru

   endrule

 

    

   //-----------------------------------------------------------

   // Methods

 

   interface Client imem_client;

     interface Get request  = fifoToGet(instReqQ);

     interface Put response = fifoToPut(instRespQ);

   endinterface

 

   interface Client dmem_client;

     interface Get request  = fifoToGet(dataReqQ);

     interface Put response = fifoToPut(dataRespQ);

   endinterface

 

   interface Get statsEn_get = toGet(asReg(cp0_statsEn));

 

   /*

   interface CPUToHost tohost;

     method Bit#(32) cpuToHost(int req);

       return (case (req)

        0: cp0_tohost;

        1: pc;

        2: zeroExtend(pack(stage));

       endcase);

     endmethod

   endinterface

   */

    

   interface Get sampleOutput = fifoToGet(outAudioFifo);

   interface Put sampleInput = fifoToPut(inAudioFifo);

   interface Get pcCount = toGet(asReg(pc));

 

 endmodule