view modules/bluespec/Pygar/lab4/BranchPred.bsv @ 65:cf8bb3038cbd pygar svn.66

[svn r66] sim passes
author punk
date Tue, 11 May 2010 09:05:22 -0400
parents 74716e9a81cc
children
line wrap: on
line source
1 import RegFile::*;
2 import ProcTypes::*;
3 import FIFO::*;
5 typedef Maybe#(Addr) BrPred;
6 typedef Bit#(4) BPindx;
8 typedef struct {Addr brpc; Addr nextpc;} BrPair deriving (Bits,Eq);
10 typedef union tagged
11 {
12 BrPair Valid;
13 void Invalid;
14 } CBranchPath deriving(Bits, Eq); // have the cache start out invalid and add valid values.
16 interface BranchPred;
17 method BrPred get(Addr pres); //returns a maybe type that is invalid if no predition
18 method Action upd(Addr pres, Addr next);
19 endinterface
21 module mkBranchPred(BranchPred);
23 //state variables
24 RegFile#(BPindx, CBranchPath) bcache <- mkRegFileFull(); // cache to hold 16 (based on BPindx)
26 method Action upd(Addr pres, Addr next);
27 BrPair brp;
28 brp = BrPair {brpc:pres, nextpc:next};
29 bcache.upd(pres[5:2], tagged Valid brp);
30 endmethod
32 method BrPred get(Addr prespc);
33 BPindx rd = prespc[5:2];
34 let cbp = bcache.sub(rd);
35 if (cbp matches tagged Valid .bp &&& bp.brpc == prespc) //make sure that the read value was actually put there and the full address matches
36 return tagged Valid bp.nextpc;
37 else return Invalid;
38 endmethod
40 endmodule