Mercurial > pygar

     1 import RegFile::*;

     2 import RWire::*;

     3 import ProcTypes::*;

     4 

     5 `include "asim/provides/low_level_platform_interface.bsh"

     6 `include "asim/provides/soft_connections.bsh"

     7 `include "asim/provides/fpga_components.bsh"

     8 `include "asim/provides/common_services.bsh"

     9 

    10 //-----------------------------------------------------------

    11 // Register file module

    12 //-----------------------------------------------------------

    13 

    14 interface BRFile;

    15    method Action   wr( Rindx rindx, Bit#(32) data );

    16    method Action Value Bit#(32) rd1( Rindx rindx );

    17    method Action Value Bit#(32) rd2( Rindx rindx );

    18 endinterface

    19 

    20 (* doc = "synthesis attribute ram_style mkBRegFile distributed;" *)

    21 (* synthesize *)

    22 module mkBRegFile(BRFile) 

    23    provisos (Bits#(index_t, size_index),

    24 	     Bits#(data_t, size_data),

    25 	     Eq#(index_t),

    26 	     Bounded#(index_t) );

    27 

    28    LUTRAM#(index_t, data_t) rf <- mkLUTRAMU_RegFile();

    29    RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire();

    30 

    31    method Action wr( Rindx rindx, Bit#(32) data );

    32       rf.upd( rindx, data );

    33       rw.wset(tuple2(rindex,data));

    34    endmethod

    35 

    36    method Bit#(32) rd1 (Rindx r);

    37       if (r == 0) return 0;

    38       else begin

    39             case (rw.wget()) matches

    40 	     tagged Valid {.wr, .d} :

    41 	       return (wr == r) ? d : rf.sub(r);

    42 	     tagged Invalid : return rf.sub(r);

    43      	    endcase

    44 	   end

    45    endmethod

    46 

    47    method Bit#(32) rd2 (Rindx r);

    48       if (r == 0) return 0;

    49       else begin

    50             case (rw.wget()) matches

    51 	     tagged Valid {.wr, .d} :

    52 	       return (wr == r) ? d : rf.sub(r);

    53 	     tagged Invalid : return rf.sub(r);

    54      	    endcase

    55 	   end

    56    endmethod

    57    

    58 endmodule
author	punk
date	Mon, 10 May 2010 21:00:49 -0400
parents	6179c07c21d7
children	1d5cbb5343d2