Mercurial > pygar
view common/BranchPred.bsv @ 62:90fa9b289aab pygar svn.63
[svn r63] synthesis boundaries
author | punk |
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date | Mon, 10 May 2010 21:00:49 -0400 |
parents | 91a1f76ddd62 |
children |
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1 import RegFile::*;2 import ProcTypes::*;3 import FIFO::*;5 typedef Maybe#(Addr) BrPred;6 typedef Bit#(4) BPindx;8 typedef struct {Addr brpc; Addr nextpc;} BrPair deriving (Bits,Eq);10 typedef union tagged11 {12 BrPair Valid;13 void Invalid;14 } CBranchPath deriving(Bits, Eq); // have the cache start out invalid and add valid values.16 interface BranchPred;17 method BrPred get(Addr pres); //returns a maybe type that is invalid if no predition18 method Action upd(Addr pres, Addr next);19 endinterface21 module mkBranchPred(BranchPred);23 //state variables24 RegFile#(BPindx, CBranchPath) bcache <- mkRegFileFull(); // cache to hold 16 (based on BPindx)26 method Action upd(Addr pres, Addr next);27 BrPair brp;28 brp = BrPair {brpc:pres, nextpc:next};29 bcache.upd(pres[5:2], tagged Valid brp);30 endmethod32 method BrPred get(Addr prespc);33 BPindx rd = prespc[5:2];34 let cbp = bcache.sub(rd);35 if (cbp matches tagged Valid .bp &&& bp.brpc == prespc) //make sure that the read value was actually put there and the full address matches36 return tagged Valid bp.nextpc;37 else return Invalid;38 endmethod40 endmodule