view modules/bluespec/Pygar/lab4/ProcessorSystem.bsv @ 42:ced2ebd41347 pygar svn.43

[svn r43] bunch of updates that almost work...
author punk
date Wed, 05 May 2010 01:09:09 -0400
parents 74716e9a81cc
children
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1 // The MIT License
3 // Copyright (c) 2009 Massachusetts Institute of Technology
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
23 import Connectable::*;
24 import GetPut::*;
25 import ClientServer::*;
26 import FIFO::*;
27 import SpecialFIFOs::*;
29 //AWB includes
30 `include "asim/provides/low_level_platform_interface.bsh"
31 `include "asim/provides/soft_connections.bsh"
32 `include "asim/provides/common_services.bsh"
35 // Local includes
36 `include "asim/provides/core.bsh"
37 `include "asim/provides/processor_library.bsh"
38 `include "asim/provides/processor_library.bsh"
39 `include "asim/provides/fpga_components.bsh"
40 `include "asim/rrr/remote_client_stub_PROCESSORSYSTEMRRR.bsh"
42 module [CONNECTED_MODULE] mkConnectedApplication ();
44 Core core <- mkCore;
45 Reg#(int) cycle <- mkReg(0);
47 //External memory
48 // I'm not comfortable assuming that the memory subsystem is in order
49 // So I'll insert a completion buffer here.
50 ClientStub_PROCESSORSYSTEMRRR client_stub <- mkClientStub_PROCESSORSYSTEMRRR();
51 // Make this big enough so that several outstanding requests may be supported
52 FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
54 // this is for the tracing
55 rule printCycles;
56 cycle <= cycle+1;
57 $fdisplay(stderr, " => Cycle = %d", cycle);
58 endrule
61 rule sendMemReq;
62 let coreReq <- core.mmem_client.request.get;
63 case (coreReq) matches
64 tagged LoadReq .load: begin
65 //Allocate ROB space
66 client_stub.makeRequest_MemoryRequestLoad(load.addr);
67 tags.enq(load.tag);
68 end
69 tagged StoreReq .store: begin
70 client_stub.makeRequest_MemoryRequestStore(store.addr,store.data);
71 end
72 endcase
73 endrule
75 rule receiveMemResp;
76 let memResp <- client_stub.getResponse_MemoryRequestLoad();
77 tags.deq;
78 core.mmem_client.response.put(tagged LoadResp {data:memResp,
79 tag: tags.first});
80 endrule
82 endmodule