view core/sim/bdir_dut/Core.bi @ 25:220c14f5963c pygar svn.26

[svn r26] Not fully connected but passes audio successfully
author punk
date Wed, 28 Apr 2010 12:01:37 -0400
parents 91a1f76ddd62
children
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1 signature Core where {
2 import ¶Assert®¶;
4 import ¶ConfigReg®¶;
6 import ¶Counter®¶;
8 import ¶FIFOF_®¶;
10 import ¶FIFOF®¶;
12 import ¶FIFO®¶;
14 import ¶Inout®¶;
16 import ¶List®¶;
18 import BFIFO;
20 import ¶Clocks®¶;
22 import ¶ListN®¶;
24 import ¶Monad®¶;
26 import ¶PrimArray®¶;
28 import ¶RWire®¶;
30 import ¶RegFile®¶;
32 import SFIFO;
34 import ¶Vector®¶;
36 import ¶Connectable®¶;
38 import ¶GetPut®¶;
40 import ¶ClientServer®¶;
42 import Trace;
44 import MemTypes;
46 import MemArb;
48 import ProcTypes;
50 import BRegFile;
52 import BranchPred;
54 import DataCacheBlocking;
56 import InstCacheBlocking;
58 import Processor;
60 interface (Core.CoreStats :: *) = {
61 Core.dcache :: DataCacheBlocking.DCacheStats;
62 Core.icache :: InstCacheBlocking.ICacheStats;
63 Core.proc :: Processor.ProcStats
64 };
66 instance Core ¶Prelude®¶.¶PrimMakeUndefined®¶ Core.CoreStats;
68 instance Core ¶Prelude®¶.¶PrimDeepSeqCond®¶ Core.CoreStats;
70 instance Core ¶Prelude®¶.¶PrimMakeUninitialized®¶ Core.CoreStats;
72 interface (Core.Core :: *) = {
73 Core.mmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.MainMemReq MemTypes.MainMemResp;
74 Core.stats :: Core.CoreStats;
75 Core.tohost :: Processor.CPUToHost
76 };
78 instance Core ¶Prelude®¶.¶PrimMakeUndefined®¶ Core.Core;
80 instance Core ¶Prelude®¶.¶PrimDeepSeqCond®¶ Core.Core;
82 instance Core ¶Prelude®¶.¶PrimMakeUninitialized®¶ Core.Core;
84 Core.mkCore :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ Core.Core
85 }