Mercurial > pygar
view modules/bluespec/Pygar/core/MemArb.bsv @ 26:f5dfbe28fa59 pygar svn.27
[svn r27] Fixed Instruction trace issue.
author | punk |
---|---|
date | Fri, 30 Apr 2010 09:03:10 -0400 |
parents | 74716e9a81cc |
children |
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1 // The MIT License3 // Copyright (c) 2009 Massachusetts Institute of Technology5 // Permission is hereby granted, free of charge, to any person obtaining a copy6 // of this software and associated documentation files (the "Software"), to deal7 // in the Software without restriction, including without limitation the rights8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell9 // copies of the Software, and to permit persons to whom the Software is10 // furnished to do so, subject to the following conditions:12 // The above copyright notice and this permission notice shall be included in13 // all copies or substantial portions of the Software.15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN21 // THE SOFTWARE.23 import Connectable::*;24 import GetPut::*;25 import ClientServer::*;26 import FIFOF::*;27 import FIFO::*;29 import BFIFO::*;30 import MemTypes::*;31 import Trace::*;33 interface MemArb;35 interface Server#(MainMemReq,MainMemResp) cache0_server;36 interface Server#(MainMemReq,MainMemResp) cache1_server;37 interface Client#(MainMemReq,MainMemResp) mmem_client;39 endinterface41 typedef enum { REQ0, REQ1 } ReqPtr deriving(Eq,Bits);43 (* synthesize *)44 module mkMemArb( MemArb );46 //-----------------------------------------------------------47 // State49 FIFOF#(MainMemReq) req0Q <- mkFIFOF1();50 FIFO#(MainMemResp) resp0Q <- mkFIFO1();52 FIFOF#(MainMemReq) req1Q <- mkFIFOF1();53 FIFO#(MainMemResp) resp1Q <- mkFIFO1();55 FIFO#(MainMemReq) mreqQ <- mkFIFO1();56 FIFO#(MainMemResp) mrespQ <- mkFIFO1();58 Reg#(ReqPtr) nextReq <- mkReg(REQ0);60 //-----------------------------------------------------------61 // Some wires63 let req0avail = req0Q.notEmpty();64 let req1avail = req1Q.notEmpty();66 //-----------------------------------------------------------67 // Rules69 rule chooseReq0 ( req0avail && (!req1avail || (nextReq == REQ0)) );70 traceTiny("mkMemArb", "memArb req0",req0Q.first());72 // Rewrite tag field if this is a load ...73 MainMemReq mreq74 = case ( req0Q.first() ) matches75 tagged LoadReq .ld : return LoadReq { tag:0, addr:ld.addr };76 tagged StoreReq .st : return req0Q.first();77 endcase;79 // Send out the request80 mreqQ.enq(mreq);81 nextReq <= REQ1;82 req0Q.deq();84 endrule86 rule chooseReq1 ( req1avail && (!req0avail || (nextReq == REQ1)) );87 traceTiny("mkMemArb", "memArb req1",req1Q.first);89 // Rewrite tag field if this is a load ...90 MainMemReq mreq91 = case ( req1Q.first() ) matches92 tagged LoadReq .ld : return LoadReq { tag:1, addr:ld.addr };93 tagged StoreReq .st : return req1Q.first();94 endcase;96 // Send out the request97 mreqQ.enq(mreq);98 nextReq <= REQ0;99 req1Q.deq();101 endrule103 rule returnResp;104 traceTiny("mkMemArb", "resp",mrespQ.first());106 // Use tag to figure out where to send response107 mrespQ.deq();108 let tag109 = case ( mrespQ.first() ) matches110 tagged LoadResp .ld : return ld.tag;111 tagged StoreResp .st : return st.tag;112 endcase;114 if ( tag == 0 )115 resp0Q.enq(mrespQ.first());116 else117 resp1Q.enq(mrespQ.first());119 endrule121 //-----------------------------------------------------------122 // Methods124 interface Server cache0_server;125 interface Put request = toPut(req0Q);126 interface Get response = toGet(resp0Q);127 endinterface129 interface Server cache1_server;130 interface Put request = toPut(req1Q);131 interface Get response = toGet(resp1Q);132 endinterface134 interface Client mmem_client;135 interface Get request = toGet(mreqQ);136 interface Put response = toPut(mrespQ);137 endinterface139 endmodule