Mercurial > pygar
view modules/bluespec/Pygar/core/audioCore.bsv @ 31:f41eef1bebfc pygar svn.32
[svn r32] Attempting to run soft core and audio
author | punk |
---|---|
date | Sat, 01 May 2010 11:50:20 -0400 |
parents | f5dfbe28fa59 |
children | 99519a031813 |
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1 // The MIT License3 // Copyright (c) 2009 Massachusetts Institute of Technology5 // Permission is hereby granted, free of charge, to any person obtaining a copy6 // of this software and associated documentation files (the "Software"), to deal7 // in the Software without restriction, including without limitation the rights8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell9 // copies of the Software, and to permit persons to whom the Software is10 // furnished to do so, subject to the following conditions:12 // The above copyright notice and this permission notice shall be included in13 // all copies or substantial portions of the Software.15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN21 // THE SOFTWARE.23 import Connectable::*;24 import GetPut::*;25 import ClientServer::*;26 import Processor::*;27 import MemArb::*;28 import MemTypes::*;30 //AWB includes31 `include "asim/provides/low_level_platform_interface.bsh"32 `include "asim/provides/soft_connections.bsh"33 `include "asim/provides/common_services.bsh"35 // Local includes36 `include "asim/provides/processor_library.bsh"37 `include "asim/provides/mem_arb.bsh"38 `include "asim/provides/instruction_cache.bsh"39 `include "asim/provides/data_cache.bsh"40 `include "asim/provides/processor.bsh"41 `include "asim/provides/audio_pipe_types.bsh"43 interface Core;45 // Interface from core to main memory46 interface Client#(MainMemReq,MainMemResp) mmem_client;48 interface Get#(AudioProcessorUnit) sampleOutput;50 endinterface52 module [CONNECTED_MODULE] mkCore( Core );54 // Instantiate the modules56 Proc proc <- mkProc();57 ICache#(InstReq,InstResp) icache <- mkInstCache();58 DCache#(DataReq,DataResp) dcache <- mkDataCache();59 MemArb marb <- mkMemArb();61 // Internal connections63 mkConnection( proc.statsEn_get, icache.statsEn_put );64 mkConnection( proc.statsEn_get, dcache.statsEn_put );65 mkConnection( proc.imem_client, icache.proc_server );66 mkConnection( proc.dmem_client, dcache.proc_server );67 mkConnection( icache.mmem_client, marb.cache0_server );68 mkConnection( dcache.mmem_client, marb.cache1_server );70 // Methods72 interface mmem_client = marb.mmem_client;74 interface sampleOutput = proc.sampleOutput;76 endmodule