Mercurial > pygar
view core/scemi/SceMiLayer.bsv @ 31:f41eef1bebfc pygar svn.32
[svn r32] Attempting to run soft core and audio
author | punk |
---|---|
date | Sat, 01 May 2010 11:50:20 -0400 |
parents | 91a1f76ddd62 |
children |
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2 import ClientServer::*;3 import FIFO::*;4 import GetPut::*;5 import DefaultValue::*;6 import SceMi::*;7 import Clocks::*;9 import Core::*;10 import ProcTypes::*;11 import Processor::*;12 import DataCacheBlocking::*;13 import InstCacheBlocking::*;15 interface DutWrapper;16 interface Core core;18 // We use a Bit#(1) instead of void because Bluespec Sce-Mi doesn't appear19 // to support sending void over the PCIe link yet.20 interface Put#(Bit#(1)) doreset;21 endinterface23 (* synthesize *)24 module [Module] mkDutWrapper (DutWrapper);26 Clock clk <- exposeCurrentClock;27 MakeResetIfc myrst <- mkReset(2000, True, clk);29 Core coreifc <- mkCore(reset_by myrst.new_rst);31 // For tracing32 Reg#(int) cycle <- mkReg(0);33 rule printCycles;34 cycle <= cycle + 1;35 $fdisplay(stderr, " => Cycle = %d", cycle);36 endrule38 interface Core core = coreifc;40 interface Put doreset;41 method Action put(Bit#(1) x);42 cycle <= 0;43 myrst.assertReset();44 endmethod45 endinterface47 endmodule49 module [SceMiModule] mkSceMiLayer();51 SceMiClockConfiguration conf = defaultValue;53 SceMiClockPortIfc clk_port <- mkSceMiClockPort(conf);54 DutWrapper dut <- buildDut(mkDutWrapper, clk_port);56 Empty mmem <- mkClientXactor(dut.core.mmem_client, clk_port);57 Empty tohost <- mkCPUToHostXactor(dut.core.tohost, clk_port);58 Empty stats <- mkCoreStatsXactor(dut.core.stats, clk_port);59 Empty doreset <- mkPutXactor(dut.doreset, clk_port);61 Empty shutdown <- mkShutdownXactor();63 endmodule65 module [SceMiModule] mkCPUToHostXactor#(CPUToHost tohost, SceMiClockPortIfc clk_port ) (Empty);67 // Access the controlled clock and reset68 Clock cclock = clk_port.cclock;69 Reset creset = clk_port.creset;71 // req belongs entirely to the controlled clock domain. We'll use the72 // clock domain crossings already implemented by the Bluespec people (in73 // the Put and Get transactors), because they know about such things74 // better than I do.75 FIFO#(int) req <- mkFIFO(clocked_by cclock, reset_by creset);77 Get#(Bit#(32)) resp = interface Get;78 method ActionValue#(Bit#(32)) get();79 req.deq();80 return tohost.cpuToHost(req.first());81 endmethod82 endinterface;84 Empty request <- mkPutXactor(toPut(req), clk_port);85 Empty response <- mkGetXactor(resp, clk_port);87 endmodule89 typedef enum {90 DCACHE_ACCESSES, DCACHE_MISSES, DCACHE_WRITEBACKS,91 ICACHE_ACCESSES, ICACHE_MISSES, ICACHE_EVICTIONS,92 PROC_INST, PROC_CYCLES93 } StatID deriving(Bits, Eq);95 module [SceMiModule] mkCoreStatsXactor#(CoreStats stats, SceMiClockPortIfc clk_port) (Empty);97 // Access the controlled clock and reset98 Clock cclock = clk_port.cclock;99 Reset creset = clk_port.creset;101 // Again, req and resp belong to the controlled clock domain.102 FIFO#(StatID) req <- mkFIFO(clocked_by cclock, reset_by creset);103 FIFO#(Stat) resp <- mkFIFO(clocked_by cclock, reset_by creset);105 rule handleRequest (True);106 case (req.first())107 DCACHE_ACCESSES: begin108 let x <- stats.dcache.num_accesses.get();109 resp.enq(x);110 end111 DCACHE_MISSES: begin112 let x <- stats.dcache.num_misses.get();113 resp.enq(x);114 end115 DCACHE_WRITEBACKS: begin116 let x <- stats.dcache.num_writebacks.get();117 resp.enq(x);118 end119 ICACHE_ACCESSES: begin120 let x <- stats.icache.num_accesses.get();121 resp.enq(x);122 end123 ICACHE_MISSES: begin124 let x <- stats.icache.num_misses.get();125 resp.enq(x);126 end127 ICACHE_EVICTIONS: begin128 let x <- stats.icache.num_evictions.get();129 resp.enq(x);130 end131 PROC_INST: begin132 let x <- stats.proc.num_inst.get();133 resp.enq(x);134 end135 PROC_CYCLES: begin136 let x <- stats.proc.num_cycles.get();137 resp.enq(x);138 end139 endcase140 req.deq();141 endrule143 Server#(StatID, Stat) server = interface Server;144 interface Get response = toGet(resp);145 interface Put request = toPut(req);146 endinterface;148 Empty xx <- mkServerXactor(server, clk_port);149 endmodule