view core/sim/bdir_dut/InstCacheBlocking.bi @ 65:cf8bb3038cbd pygar svn.66

[svn r66] sim passes
author punk
date Tue, 11 May 2010 09:05:22 -0400
parents 91a1f76ddd62
children
line wrap: on
line source
1 signature InstCacheBlocking where {
2 import ¶Assert®¶;
4 import ¶Counter®¶;
6 import ¶FIFOF_®¶;
8 import ¶FIFOF®¶;
10 import ¶FIFO®¶;
12 import ¶Inout®¶;
14 import ¶List®¶;
16 import BFIFO;
18 import ¶Clocks®¶;
20 import ¶ListN®¶;
22 import ¶PrimArray®¶;
24 import ¶RWire®¶;
26 import ¶RegFile®¶;
28 import ¶Vector®¶;
30 import ¶Connectable®¶;
32 import ¶GetPut®¶;
34 import ¶ClientServer®¶;
36 import Trace;
38 import MemTypes;
40 import ProcTypes;
42 interface (InstCacheBlocking.ICacheStats :: *) = {
43 InstCacheBlocking.num_accesses :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat;
44 InstCacheBlocking.num_misses :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat;
45 InstCacheBlocking.num_evictions :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat
46 };
48 instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUndefined®¶ InstCacheBlocking.ICacheStats;
50 instance InstCacheBlocking ¶Prelude®¶.¶PrimDeepSeqCond®¶ InstCacheBlocking.ICacheStats;
52 instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ InstCacheBlocking.ICacheStats;
54 interface (InstCacheBlocking.ICache :: * -> * -> *) req_t resp_t = {
55 InstCacheBlocking.proc_server :: ¶ClientServer®¶.¶Server®¶ req_t resp_t;
56 InstCacheBlocking.mmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.MainMemReq MemTypes.MainMemResp;
57 InstCacheBlocking.statsEn_put :: ¶GetPut®¶.¶Put®¶ ¶Prelude®¶.¶Bool®¶;
58 InstCacheBlocking.stats :: InstCacheBlocking.ICacheStats
59 };
61 instance InstCacheBlocking (¶Prelude®¶.¶PrimMakeUndefined®¶ resp_t) =>
62 ¶Prelude®¶.¶PrimMakeUndefined®¶ (InstCacheBlocking.ICache req_t resp_t);
64 instance InstCacheBlocking (¶Prelude®¶.¶PrimDeepSeqCond®¶ resp_t) =>
65 ¶Prelude®¶.¶PrimDeepSeqCond®¶ (InstCacheBlocking.ICache req_t resp_t);
67 instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶
68 (InstCacheBlocking.ICache req_t resp_t);
70 type (InstCacheBlocking.CacheLineIndexSz :: #) = 10;
72 type (InstCacheBlocking.CacheLineTagSz :: #) = 20;
74 type (InstCacheBlocking.CacheLineSz :: #) = 32;
76 type (InstCacheBlocking.CacheLineIndex :: *) = ¶Prelude®¶.¶Bit®¶ InstCacheBlocking.CacheLineIndexSz;
78 type (InstCacheBlocking.CacheLineTag :: *) = ¶Prelude®¶.¶Bit®¶ InstCacheBlocking.CacheLineTagSz;
80 type (InstCacheBlocking.CacheLine :: *) = ¶Prelude®¶.¶Bit®¶ InstCacheBlocking.CacheLineSz;
82 data (InstCacheBlocking.CacheStage :: *) =
83 InstCacheBlocking.Init () |
84 InstCacheBlocking.Access () |
85 InstCacheBlocking.Evict () |
86 InstCacheBlocking.RefillReq () |
87 InstCacheBlocking.RefillResp ();
89 instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUndefined®¶ InstCacheBlocking.CacheStage;
91 instance InstCacheBlocking ¶Prelude®¶.¶PrimDeepSeqCond®¶ InstCacheBlocking.CacheStage;
93 instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ InstCacheBlocking.CacheStage;
95 instance InstCacheBlocking ¶Prelude®¶.¶Eq®¶ InstCacheBlocking.CacheStage;
97 instance InstCacheBlocking ¶Prelude®¶.¶Bits®¶ InstCacheBlocking.CacheStage 3;
99 InstCacheBlocking.getAddr :: MemTypes.InstReq -> ¶Prelude®¶.¶Bit®¶ MemTypes.AddrSz;
101 InstCacheBlocking.getCacheLineIndex :: MemTypes.InstReq -> InstCacheBlocking.CacheLineIndex;
103 InstCacheBlocking.getCacheLineTag :: MemTypes.InstReq -> InstCacheBlocking.CacheLineTag;
105 InstCacheBlocking.getCacheLineAddr :: MemTypes.InstReq -> ¶Prelude®¶.¶Bit®¶ MemTypes.AddrSz;
107 InstCacheBlocking.mkInstCache :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) =>
108 _m__ (InstCacheBlocking.ICache MemTypes.InstReq MemTypes.InstResp)
109 }