Mercurial > pygar

     1 // The MIT License

     2 

     3 // Copyright (c) 2009 Massachusetts Institute of Technology

     4 

     5 // Permission is hereby granted, free of charge, to any person obtaining a copy

     6 // of this software and associated documentation files (the "Software"), to deal

     7 // in the Software without restriction, including without limitation the rights

     8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

     9 // copies of the Software, and to permit persons to whom the Software is

    10 // furnished to do so, subject to the following conditions:

    11 

    12 // The above copyright notice and this permission notice shall be included in

    13 // all copies or substantial portions of the Software.

    14 

    15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

    16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

    17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

    18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

    19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

    20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

    21 // THE SOFTWARE.

    22 

    23 // Author: Kermin Fleming kfleming@mit.edu

    24 

    25 import Connectable::*;

    26 import GetPut::*;

    27 import ClientServer::*;

    28 import FIFO::*;

    29 import SpecialFIFOs::*;

    30 

    31 //AWB includes

    32 `include "asim/provides/low_level_platform_interface.bsh"

    33 `include "asim/provides/soft_connections.bsh"

    34 `include "asim/provides/common_services.bsh"

    35 

    36 //Local includes

    37 `include "asim/provides/audio_pipe_types.bsh"  //provides Audio Pipeline interface

    38 `include "asim/provides/core.bsh"

    39 `include "asim/provides/processor_library.bsh"

    40 `include "asim/provides/fpga_components.bsh"

    41 `include "asim/provides/scratchpad_memory.bsh"

    42 `include "asim/provides/mem_services.bsh"

    43 `include "asim/dict/VDEV_SCRATCH.bsh"

    44 

    45 `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"

    46 //`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"

    47 

    48 module [CONNECTED_MODULE] mkConnectedApplication ();

    49    Core core <- mkCore;

    50    Reg#(int) cycle <- mkReg(0);

    51 

    52    //mkMixer();

    53    

    54   //External memory 

    55   // I'm not comfortable assuming that the memory subsystem is in order  

    56   // So I'll insert a completion buffer here.

    57   MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED);   //Services Memory items

    58 

    59   // Services Samples 

    60   ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR();   

    61   // Make this big enough so that several outstanding requests may be supported

    62   FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);

    63 

    64   // this is for the tracing

    65   rule printCycles;

    66     cycle <= cycle+1;

    67     $fdisplay(stderr, " => Cycle = %d", cycle);

    68   endrule

    69 

    70   rule sendMemReq;

    71     let coreReq <- core.mmem_client.request.get;

    72     case (coreReq) matches 

    73       tagged LoadReq .load: begin

    74                               //Allocate ROB space

    75                               memory.readReq(truncate(load.addr>>2));

    76                               tags.enq(load.tag);

    77                             end

    78       tagged StoreReq .store: begin

    79 	                      memory.write(truncate(store.addr>>2),store.data);

    80                               end

    81     endcase

    82   endrule

    83   

    84   rule receiveMemResp;

    85     let memResp <- memory.readRsp();

    86     tags.deq;

    87     core.mmem_client.response.put(tagged LoadResp {data:memResp,

    88                                                    tag: tags.first});

    89   endrule

    90 

    91    rule feedOutput;

    92      let pipelineData <- core.sampleOutput.get();

    93      AudioProcessorControl endOfFileTag = EndOfFile;

    94      AudioProcessorControl sampleTag = Data;

    95 

    96      case (pipelineData) matches

    97        tagged EndOfFile: 

    98        client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?);

    99        tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)), zeroExtend(pack(sample)));

   100      endcase

   101    endrule

   102 

   103 endmodule
author	rlm
date	Wed, 12 May 2010 00:14:01 -0400
parents	2c8166d205d5
children