Mercurial > pygar
view modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv @ 57:b5be746a0d74 pygar svn.58
[svn r58] removed throttle in main
author | punk |
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date | Mon, 10 May 2010 12:17:52 -0400 |
parents | 9fe5ed4af92d |
children | 6179c07c21d7 |
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1 // The MIT License3 // Copyright (c) 2009 Massachusetts Institute of Technology5 // Permission is hereby granted, free of charge, to any person obtaining a copy6 // of this software and associated documentation files (the "Software"), to deal7 // in the Software without restriction, including without limitation the rights8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell9 // copies of the Software, and to permit persons to whom the Software is10 // furnished to do so, subject to the following conditions:12 // The above copyright notice and this permission notice shall be included in13 // all copies or substantial portions of the Software.15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN21 // THE SOFTWARE.23 // Local includes24 `include "asim/provides/low_level_platform_interface.bsh"25 `include "asim/provides/soft_connections.bsh"26 `include "asim/provides/processor_library.bsh"27 `include "asim/provides/fpga_components.bsh"28 `include "asim/provides/common_services.bsh"30 import Connectable::*;31 import GetPut::*;32 import ClientServer::*;33 import RegFile::*;34 import FIFO::*;35 import FIFOF::*;36 import Trace::*;38 interface DCache#( type req_t, type resp_t );40 // Interface from processor to cache41 interface Server#(req_t,resp_t) proc_server;43 // Interface from cache to main memory44 interface Client#(MainMemReq,MainMemResp) mmem_client;46 // Interface for enabling/disabling statistics47 interface Put#(Bool) statsEn_put;49 endinterface52 //----------------------------------------------------------------------53 // Cache Types54 //----------------------------------------------------------------------56 typedef 10 CacheLineIndexSz;57 typedef 20 CacheLineTagSz;58 typedef 32 CacheLineSz;60 typedef Bit#(CacheLineIndexSz) CacheLineIndex;61 typedef Bit#(CacheLineTagSz) CacheLineTag;62 typedef Bit#(CacheLineSz) CacheLine;64 typedef enum65 {66 Init,67 Access,68 RefillReq,69 RefillResp70 }71 CacheStage72 deriving (Eq,Bits);74 //----------------------------------------------------------------------75 // Helper functions76 //----------------------------------------------------------------------78 function Bit#(AddrSz) getAddr( DataReq req );80 Bit#(AddrSz) addr = ?;81 case ( req ) matches82 tagged LoadReq .ld : addr = ld.addr;83 tagged StoreReq .st : addr = st.addr;84 endcase86 return addr;88 endfunction90 function CacheLineIndex getCacheLineIndex( DataReq req );91 Bit#(AddrSz) addr = getAddr(req);92 Bit#(CacheLineIndexSz) index = truncate( addr >> 2 );93 return index;94 endfunction96 function CacheLineTag getCacheLineTag( DataReq req );97 Bit#(AddrSz) addr = getAddr(req);98 Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 );99 return tag;100 endfunction102 function Bit#(AddrSz) getCacheLineAddr( DataReq req );103 Bit#(AddrSz) addr = getAddr(req);104 return ((addr >> 2) << 2);105 endfunction107 //----------------------------------------------------------------------108 // Main module109 //----------------------------------------------------------------------111 module [CONNECTED_MODULE] mkDataCache( DCache#(DataReq,DataResp) );113 //-----------------------------------------------------------114 // State116 Reg#(CacheStage) stage <- mkReg(Init);118 LUTRAM#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkLUTRAMU_RegFile();119 LUTRAM#(CacheLineIndex,CacheLine) cacheDataRam <- mkLUTRAMU_RegFile();121 FIFO#(DataReq) reqQ <- mkFIFO();122 FIFOF#(DataResp) respQ <- mkBFIFOF1();124 FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1();125 FIFO#(MainMemResp) mainMemRespQ <- mkFIFO();127 Reg#(CacheLineIndex) initCounter <- mkReg(1);129 // Statistics state131 Reg#(Bool) statsEn <- mkReg(False);132 //rlm:133 //STAT num_accesses <- mkStatCounter(`STATS_DATA_CACHE_NUM_ACCESSES);134 //STAT num_misses <- mkStatCounter(`STATS_DATA_CACHE_NUM_MISSES);135 //STAT num_writebacks <- mkStatCounter(`STATS_DATA_CACHE_NUM_WRITEBACKS);137 //-----------------------------------------------------------138 // Name some wires140 let req = reqQ.first();141 let reqIndex = getCacheLineIndex(req);142 let reqTag = getCacheLineTag(req);143 let reqCacheLineAddr = getCacheLineAddr(req);145 //-----------------------------------------------------------146 // Initialize148 rule init ( stage == Init );149 traceTiny("mkDataCacheBlocking", "stage","i");150 initCounter <= initCounter + 1;151 cacheTagRam.upd(initCounter,Invalid);152 if ( initCounter == 0 )153 stage <= Access;154 endrule156 //-----------------------------------------------------------157 // Access cache rule159 rule access ( (stage == Access) && respQ.notFull() );161 // Statistics162 //rlm:163 //if ( statsEn )164 // num_accesses.incr();167 // Get the corresponding tag from the rams169 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);171 // Handle cache hits ...173 if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) )174 begin175 traceTiny("mkDataCacheBlocking", "hitMiss","h");176 reqQ.deq();178 case ( req ) matches180 tagged LoadReq .ld :181 respQ.enq( LoadResp { tag: ld.tag, data: cacheDataRam.sub(reqIndex) } );183 tagged StoreReq .st :184 begin185 respQ.enq( StoreResp { tag : st.tag } );186 cacheDataRam.upd(reqIndex,st.data);187 end189 endcase191 end193 // Handle cache misses ...195 else196 begin197 traceTiny("mkDataCacheBlocking", "hitMiss","m");198 //rlm:199 //if ( statsEn )200 // num_misses.incr();202 // Currently we don't use dirty bits so we always writeback the data if it is valid204 if ( isValid(cacheLineTag) )205 begin206 //rlm:207 // if ( statsEn )208 // num_writebacks.incr();210 MainMemReq wbReq211 = StoreReq { tag : 0,212 addr : { unJust(cacheLineTag), reqIndex, 2'b0 },213 data : cacheDataRam.sub(reqIndex) };215 mainMemReqQ.enq(wbReq);216 stage <= RefillReq;217 end219 // Otherwise we can issue the refill request now221 else222 begin223 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } );224 stage <= RefillResp;225 end227 end229 endrule231 //-----------------------------------------------------------232 // Refill request rule234 rule refillReq ( stage == RefillReq );235 traceTiny("mkDataCacheBlocking", "stage","r");236 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } );237 stage <= RefillResp;238 endrule240 //-----------------------------------------------------------241 // Refill response rule243 rule refillResp ( stage == RefillResp );244 traceTiny("mkDataCacheBlocking", "stage","R");245 traceTiny("mkDataCacheBlocking", "refill",mainMemRespQ.first());247 // Write the new data into the cache and update the tag249 mainMemRespQ.deq();250 case ( mainMemRespQ.first() ) matches252 tagged LoadResp .ld :253 begin254 cacheTagRam.upd(reqIndex,Valid(reqTag));255 cacheDataRam.upd(reqIndex,ld.data);256 end258 tagged StoreResp .st :259 noAction;261 endcase263 stage <= Access;264 endrule266 //-----------------------------------------------------------267 // Methods269 interface Client mmem_client;270 interface Get request = fifoToGet(mainMemReqQ);271 interface Put response = fifoToPut(mainMemRespQ);272 endinterface274 interface Server proc_server;275 interface Put request = tracePut("mkDataCacheBlocking", "reqTiny",fifoToPut(reqQ));276 interface Get response = traceGet("mkDataCacheBlocking", "respTiny",fifofToGet(respQ));277 endinterface279 interface Put statsEn_put = regToPut(statsEn);281 endmodule