Mercurial > pygar
view modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv @ 19:9910c032f38d pygar svn.20
[svn r20] fixed some random reference errot
author | rlm |
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date | Tue, 27 Apr 2010 23:31:38 -0400 |
parents | 74716e9a81cc |
children | 3958de09a7c1 |
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1 // The MIT License3 // Copyright (c) 2009 Massachusetts Institute of Technology5 // Permission is hereby granted, free of charge, to any person obtaining a copy6 // of this software and associated documentation files (the "Software"), to deal7 // in the Software without restriction, including without limitation the rights8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell9 // copies of the Software, and to permit persons to whom the Software is10 // furnished to do so, subject to the following conditions:12 // The above copyright notice and this permission notice shall be included in13 // all copies or substantial portions of the Software.15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN21 // THE SOFTWARE.23 // Local includes24 `include "asim/provides/low_level_platform_interface.bsh"25 `include "asim/provides/soft_connections.bsh"26 `include "asim/provides/processor_library.bsh"27 `include "asim/provides/fpga_components.bsh"28 `include "asim/provides/common_services.bsh"29 `include "asim/dict/STATS_DATA_CACHE.bsh"31 import Connectable::*;32 import GetPut::*;33 import ClientServer::*;34 import RegFile::*;35 import FIFO::*;36 import FIFOF::*;41 interface DCache#( type req_t, type resp_t );43 // Interface from processor to cache44 interface Server#(req_t,resp_t) proc_server;46 // Interface from cache to main memory47 interface Client#(MainMemReq,MainMemResp) mmem_client;49 // Interface for enabling/disabling statistics50 interface Put#(Bool) statsEn_put;52 endinterface55 //----------------------------------------------------------------------56 // Cache Types57 //----------------------------------------------------------------------59 typedef 10 CacheLineIndexSz;60 typedef 20 CacheLineTagSz;61 typedef 32 CacheLineSz;63 typedef Bit#(CacheLineIndexSz) CacheLineIndex;64 typedef Bit#(CacheLineTagSz) CacheLineTag;65 typedef Bit#(CacheLineSz) CacheLine;67 typedef enum68 {69 Init,70 Access,71 RefillReq,72 RefillResp73 }74 CacheStage75 deriving (Eq,Bits);77 //----------------------------------------------------------------------78 // Helper functions79 //----------------------------------------------------------------------81 function Bit#(AddrSz) getAddr( DataReq req );83 Bit#(AddrSz) addr = ?;84 case ( req ) matches85 tagged LoadReq .ld : addr = ld.addr;86 tagged StoreReq .st : addr = st.addr;87 endcase89 return addr;91 endfunction93 function CacheLineIndex getCacheLineIndex( DataReq req );94 Bit#(AddrSz) addr = getAddr(req);95 Bit#(CacheLineIndexSz) index = truncate( addr >> 2 );96 return index;97 endfunction99 function CacheLineTag getCacheLineTag( DataReq req );100 Bit#(AddrSz) addr = getAddr(req);101 Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 );102 return tag;103 endfunction105 function Bit#(AddrSz) getCacheLineAddr( DataReq req );106 Bit#(AddrSz) addr = getAddr(req);107 return ((addr >> 2) << 2);108 endfunction110 //----------------------------------------------------------------------111 // Main module112 //----------------------------------------------------------------------114 module [CONNECTED_MODULE] mkDataCache( DCache#(DataReq,DataResp) );116 //-----------------------------------------------------------117 // State119 Reg#(CacheStage) stage <- mkReg(Init);121 LUTRAM#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkLUTRAMU_RegFile();122 LUTRAM#(CacheLineIndex,CacheLine) cacheDataRam <- mkLUTRAMU_RegFile();124 FIFO#(DataReq) reqQ <- mkFIFO();125 FIFOF#(DataResp) respQ <- mkBFIFOF1();127 FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1();128 FIFO#(MainMemResp) mainMemRespQ <- mkFIFO();130 Reg#(CacheLineIndex) initCounter <- mkReg(1);132 // Statistics state134 Reg#(Bool) statsEn <- mkReg(False);136 STAT num_accesses <- mkStatCounter(`STATS_DATA_CACHE_NUM_ACCESSES);137 STAT num_misses <- mkStatCounter(`STATS_DATA_CACHE_NUM_MISSES);138 STAT num_writebacks <- mkStatCounter(`STATS_DATA_CACHE_NUM_WRITEBACKS);140 //-----------------------------------------------------------141 // Name some wires143 let req = reqQ.first();144 let reqIndex = getCacheLineIndex(req);145 let reqTag = getCacheLineTag(req);146 let reqCacheLineAddr = getCacheLineAddr(req);148 //-----------------------------------------------------------149 // Initialize151 rule init ( stage == Init );152 traceTiny("mkDataCacheBlocking", "stage","i");153 initCounter <= initCounter + 1;154 cacheTagRam.upd(initCounter,Invalid);155 if ( initCounter == 0 )156 stage <= Access;157 endrule159 //-----------------------------------------------------------160 // Access cache rule162 rule access ( (stage == Access) && respQ.notFull() );164 // Statistics166 if ( statsEn )167 num_accesses.incr();170 // Get the corresponding tag from the rams172 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);174 // Handle cache hits ...176 if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) )177 begin178 traceTiny("mkDataCacheBlocking", "hitMiss","h");179 reqQ.deq();181 case ( req ) matches183 tagged LoadReq .ld :184 respQ.enq( LoadResp { tag: ld.tag, data: cacheDataRam.sub(reqIndex) } );186 tagged StoreReq .st :187 begin188 respQ.enq( StoreResp { tag : st.tag } );189 cacheDataRam.upd(reqIndex,st.data);190 end192 endcase194 end196 // Handle cache misses ...198 else199 begin200 traceTiny("mkDataCacheBlocking", "hitMiss","m");201 if ( statsEn )202 num_misses.incr();204 // Currently we don't use dirty bits so we always writeback the data if it is valid206 if ( isValid(cacheLineTag) )207 begin209 if ( statsEn )210 num_writebacks.incr();212 MainMemReq wbReq213 = StoreReq { tag : 0,214 addr : { unJust(cacheLineTag), reqIndex, 2'b0 },215 data : cacheDataRam.sub(reqIndex) };217 mainMemReqQ.enq(wbReq);218 stage <= RefillReq;219 end221 // Otherwise we can issue the refill request now223 else224 begin225 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } );226 stage <= RefillResp;227 end229 end231 endrule233 //-----------------------------------------------------------234 // Refill request rule236 rule refillReq ( stage == RefillReq );237 traceTiny("mkDataCacheBlocking", "stage","r");238 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } );239 stage <= RefillResp;240 endrule242 //-----------------------------------------------------------243 // Refill response rule245 rule refillResp ( stage == RefillResp );246 traceTiny("mkDataCacheBlocking", "stage","R");247 traceTiny("mkDataCacheBlocking", "refill",mainMemRespQ.first());249 // Write the new data into the cache and update the tag251 mainMemRespQ.deq();252 case ( mainMemRespQ.first() ) matches254 tagged LoadResp .ld :255 begin256 cacheTagRam.upd(reqIndex,Valid(reqTag));257 cacheDataRam.upd(reqIndex,ld.data);258 end260 tagged StoreResp .st :261 noAction;263 endcase265 stage <= Access;266 endrule268 //-----------------------------------------------------------269 // Methods271 interface Client mmem_client;272 interface Get request = fifoToGet(mainMemReqQ);273 interface Put response = fifoToPut(mainMemRespQ);274 endinterface276 interface Server proc_server;277 interface Put request = tracePut("mkDataCacheBlocking", "reqTiny",fifoToPut(reqQ));278 interface Get response = traceGet("mkDataCacheBlocking", "respTiny",fifofToGet(respQ));279 endinterface281 interface Put statsEn_put = regToPut(statsEn);283 endmodule