Mercurial > pygar

     1 

     2 import ClientServer::*;

     3 import FIFO::*;

     4 import GetPut::*;

     5 import DefaultValue::*;

     6 import SceMi::*;

     7 import Clocks::*;

     8 

     9 import Core::*;

    10 import ProcTypes::*;

    11 import Processor::*;

    12 import DataCacheBlocking::*;

    13 import InstCacheBlocking::*;

    14 

    15 interface DutWrapper;

    16     interface Core core;

    17 

    18     // We use a Bit#(1) instead of void because Bluespec Sce-Mi doesn't appear

    19     // to support sending void over the PCIe link yet.

    20     interface Put#(Bit#(1)) doreset;

    21 endinterface

    22 

    23 (* synthesize *)

    24 module [Module] mkDutWrapper (DutWrapper);

    25 

    26     Clock clk <- exposeCurrentClock;

    27     MakeResetIfc myrst <- mkReset(2000, True, clk);

    28 

    29     Core coreifc <- mkCore(reset_by myrst.new_rst);

    30 

    31     // For tracing

    32     Reg#(int) cycle <- mkReg(0);

    33     rule printCycles;

    34         cycle <= cycle + 1;

    35         $fdisplay(stderr, " => Cycle = %d", cycle);

    36     endrule

    37 

    38     interface Core core = coreifc;

    39 

    40     interface Put doreset;

    41         method Action put(Bit#(1) x);

    42             cycle <= 0;

    43             myrst.assertReset();

    44         endmethod

    45     endinterface

    46     

    47 endmodule

    48 

    49 module [SceMiModule] mkSceMiLayer();

    50 

    51     SceMiClockConfiguration conf = defaultValue;

    52 

    53     SceMiClockPortIfc clk_port <- mkSceMiClockPort(conf);

    54     DutWrapper dut <- buildDut(mkDutWrapper, clk_port);

    55 

    56     Empty mmem <- mkClientXactor(dut.core.mmem_client, clk_port);

    57     Empty tohost <- mkCPUToHostXactor(dut.core.tohost, clk_port);

    58     Empty stats <- mkCoreStatsXactor(dut.core.stats, clk_port);

    59     Empty doreset <- mkPutXactor(dut.doreset, clk_port);

    60 

    61     Empty shutdown <- mkShutdownXactor();

    62 

    63 endmodule

    64 

    65 module [SceMiModule] mkCPUToHostXactor#(CPUToHost tohost, SceMiClockPortIfc clk_port ) (Empty);

    66 

    67     // Access the controlled clock and reset

    68     Clock cclock = clk_port.cclock;

    69     Reset creset = clk_port.creset;

    70 

    71     // req belongs entirely to the controlled clock domain. We'll use the

    72     // clock domain crossings already implemented by the Bluespec people (in

    73     // the Put and Get transactors), because they know about such things

    74     // better than I do.

    75     FIFO#(int) req <- mkFIFO(clocked_by cclock, reset_by creset);

    76 

    77     Get#(Bit#(32)) resp = interface Get;

    78         method ActionValue#(Bit#(32)) get();

    79             req.deq();

    80             return tohost.cpuToHost(req.first());

    81         endmethod

    82     endinterface;

    83 

    84     Empty request <- mkPutXactor(toPut(req), clk_port);

    85     Empty response <- mkGetXactor(resp, clk_port);

    86 

    87 endmodule

    88 

    89 typedef enum {

    90     DCACHE_ACCESSES, DCACHE_MISSES, DCACHE_WRITEBACKS,

    91     ICACHE_ACCESSES, ICACHE_MISSES, ICACHE_EVICTIONS,

    92     PROC_INST, PROC_CYCLES

    93 } StatID deriving(Bits, Eq);

    94 

    95 module [SceMiModule] mkCoreStatsXactor#(CoreStats stats, SceMiClockPortIfc clk_port) (Empty);

    96 

    97     // Access the controlled clock and reset

    98     Clock cclock = clk_port.cclock;

    99     Reset creset = clk_port.creset;

   100 

   101     // Again, req and resp belong to the controlled clock domain.

   102     FIFO#(StatID) req <- mkFIFO(clocked_by cclock, reset_by creset);

   103     FIFO#(Stat) resp <- mkFIFO(clocked_by cclock, reset_by creset);

   104 

   105     rule handleRequest (True);

   106         case (req.first())

   107             DCACHE_ACCESSES: begin

   108                 let x <- stats.dcache.num_accesses.get();

   109                 resp.enq(x);

   110             end

   111             DCACHE_MISSES: begin

   112                 let x <- stats.dcache.num_misses.get();

   113                 resp.enq(x);

   114             end

   115             DCACHE_WRITEBACKS: begin

   116                 let x <- stats.dcache.num_writebacks.get();

   117                 resp.enq(x);

   118             end

   119             ICACHE_ACCESSES: begin

   120                 let x <- stats.icache.num_accesses.get();

   121                 resp.enq(x);

   122             end

   123             ICACHE_MISSES: begin

   124                 let x <- stats.icache.num_misses.get();

   125                 resp.enq(x);

   126             end

   127             ICACHE_EVICTIONS: begin

   128                 let x <- stats.icache.num_evictions.get();

   129                 resp.enq(x);

   130             end

   131             PROC_INST: begin

   132                 let x <- stats.proc.num_inst.get();

   133                 resp.enq(x);

   134             end

   135             PROC_CYCLES: begin

   136                 let x <- stats.proc.num_cycles.get();

   137                 resp.enq(x);

   138             end

   139         endcase

   140         req.deq();

   141     endrule

   142 

   143     Server#(StatID, Stat) server = interface Server;

   144         interface Get response = toGet(resp);

   145         interface Put request = toPut(req);

   146     endinterface;

   147 

   148     Empty xx <- mkServerXactor(server, clk_port);

   149 endmodule

   150
author	rlm
date	Wed, 12 May 2010 08:58:23 -0400
parents	91a1f76ddd62
children