view modules/bluespec/Pygar/core/audioCore.bsv @ 71:86360c5ae9f2 pygar svn.72

[svn r72] added config for htg
author punk
date Wed, 12 May 2010 00:21:40 -0400
parents 44cc00df1168
children
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1 // The MIT License
3 // Copyright (c) 2009 Massachusetts Institute of Technology
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
23 import Connectable::*;
24 import GetPut::*;
25 import ClientServer::*;
26 import Processor::*;
27 import MemArb::*;
28 import MemTypes::*;
29 import FIFO::*;
31 //AWB includes
32 `include "asim/provides/low_level_platform_interface.bsh"
33 `include "asim/provides/soft_connections.bsh"
34 `include "asim/provides/common_services.bsh"
36 // Local includes
37 `include "asim/provides/processor_library.bsh"
38 `include "asim/provides/mem_arb.bsh"
39 `include "asim/provides/instruction_cache.bsh"
40 `include "asim/provides/data_cache.bsh"
41 `include "asim/provides/processor.bsh"
42 `include "asim/provides/audio_pipe_types.bsh"
43 `include "asim/provides/path_types.bsh"
45 // Scratchpad includes
46 `include "asim/provides/scratchpad_memory.bsh"
47 `include "asim/provides/mem_services.bsh"
48 `include "asim/dict/VDEV_SCRATCH.bsh"
50 interface Core;
52 interface Get#(AudioStream) sampleOutput;
53 interface Put#(AudioStream) sampleInput;
55 interface Get#(Bit#(32)) pc;
57 endinterface
59 module [CONNECTED_MODULE] mkCore#(Integer prog) ( Core );
60 // Instantiate the modules
62 Proc proc <- mkProc();
63 ICache#(InstReq,InstResp) icache <- mkInstCache();
64 DCache#(DataReq,DataResp) dcache <- mkDataCache();
65 MemArb marb <- mkMemArb();
66 MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(prog, SCRATCHPAD_CACHED); //Services Memory items
68 // Make this big enough so that several outstanding requests may be supported
69 FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
71 // Internal connections
73 mkConnection( proc.statsEn_get, icache.statsEn_put );
74 mkConnection( proc.statsEn_get, dcache.statsEn_put );
75 mkConnection( proc.imem_client, icache.proc_server );
76 mkConnection( proc.dmem_client, dcache.proc_server );
77 mkConnection( icache.mmem_client, marb.cache0_server );
78 mkConnection( dcache.mmem_client, marb.cache1_server );
80 // Memory Access
81 rule sendMemReq;
82 let coreReq <- marb.mmem_client.request.get;
83 case (coreReq) matches
84 tagged LoadReq .load: begin
85 $display("CORE: Load Addr Req %h", load.addr);
86 //Allocate ROB space
87 memory.readReq(truncate(load.addr>>2));
88 tags.enq(load.tag);
89 end
90 tagged StoreReq .store: begin
91 $display("CORE: Write Addr Req %h", store.addr);
92 memory.write(truncate(store.addr>>2),store.data);
93 end
94 endcase
95 endrule
97 rule receiveMemResp;
98 let memResp <- memory.readRsp();
99 tags.deq;
100 marb.mmem_client.response.put(tagged LoadResp {data:memResp,
101 tag: tags.first});
102 $display("CORE: Receive MemReq %x", memResp);
103 endrule
105 // Methods
107 interface sampleOutput = proc.sampleOutput;
108 interface sampleInput = proc.sampleInput;
110 interface pc = proc.pcCount;
112 endmodule