Mercurial > pygar

     1 // The MIT License

     2 

     3 // Copyright (c) 2009 Massachusetts Institute of Technology

     4 

     5 // Permission is hereby granted, free of charge, to any person obtaining a copy

     6 // of this software and associated documentation files (the "Software"), to deal

     7 // in the Software without restriction, including without limitation the rights

     8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

     9 // copies of the Software, and to permit persons to whom the Software is

    10 // furnished to do so, subject to the following conditions:

    11 

    12 // The above copyright notice and this permission notice shall be included in

    13 // all copies or substantial portions of the Software.

    14 

    15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

    16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

    17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

    18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

    19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

    20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

    21 // THE SOFTWARE.

    22 

    23 // Author: Kermin Fleming kfleming@mit.edu

    24 

    25 import Connectable::*;

    26 import GetPut::*;

    27 import ClientServer::*;

    28 import FIFO::*;

    29 import SpecialFIFOs::*;

    30 

    31 //AWB includes

    32 `include "asim/provides/low_level_platform_interface.bsh"

    33 `include "asim/provides/soft_connections.bsh"

    34 `include "asim/provides/common_services.bsh"

    35 

    36 //Local includes

    37 `include "asim/provides/audio_pipe_types.bsh"  //provides Audio Pipeline interface

    38 `include "asim/provides/path_types.bsh"

    39 `include "asim/provides/core.bsh"

    40 `include "asim/provides/processor_library.bsh"

    41 `include "asim/provides/fpga_components.bsh"

    42 `include "asim/provides/scratchpad_memory.bsh"

    43 `include "asim/provides/mem_services.bsh"

    44 `include "asim/dict/VDEV_SCRATCH.bsh"

    45 

    46 `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"

    47 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"

    48 

    49 module [CONNECTED_MODULE] mkConnectedApplication ();

    50    Core core <- mkCore;

    51    Reg#(int) cycle <- mkReg(0);

    52 

    53 //   Reg#(Bit#(32)) ac_fini <- mkReg(0);

    54 

    55   //External memory 

    56   // I'm not comfortable assuming that the memory subsystem is in order  

    57   // So I'll insert a completion buffer here.

    58   MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED);   //Services Memory items

    59 

    60   // Services Samples 

    61   ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR();   

    62   // Make this big enough so that several outstanding requests may be supported

    63   FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);

    64 

    65    //-----------------------------------------------------------

    66    // Debug port

    67    

    68    ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR();   

    69 

    70    

    71   // this is for the tracing

    72   rule printCycles;

    73     cycle <= cycle+1;

    74     $fdisplay(stderr, " => Cycle = %d", cycle);

    75   endrule

    76 

    77   rule sendMemReq;

    78     let coreReq <- core.mmem_client.request.get;

    79     case (coreReq) matches 

    80       tagged LoadReq .load: begin

    81                               //Allocate ROB space

    82                               memory.readReq(truncate(load.addr>>2));

    83                               tags.enq(load.tag);

    84                             end

    85       tagged StoreReq .store: begin

    86 	                      memory.write(truncate(store.addr>>2),store.data);

    87                               end

    88     endcase

    89   endrule

    90   

    91   rule receiveMemResp;

    92     let memResp <- memory.readRsp();

    93     tags.deq;

    94     core.mmem_client.response.put(tagged LoadResp {data:memResp,

    95                                                    tag: tags.first});

    96   endrule

    97 

    98    rule feedOutput;

    99      let pipelineData <- core.sampleOutput.get();

   100      AudioProcessorControl endOfFileTag = EndOfFile;

   101      AudioProcessorControl sampleTag = Data;

   102 

   103      case (pipelineData) matches

   104        tagged EndOfFile: 

   105        client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?);

   106        tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)), zeroExtend(pack(sample)));

   107      endcase

   108    endrule

   109 

   110    //*****  SERVER Side  *****

   111 

   112 /*   (* conservative_implicit_conditions *)

   113   rule handleCPUToHost;

   114    let req <- server_stub.acceptRequest_ReadCPUToHost();

   115     case (req)

   116      0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);

   117     endcase

   118   endrule

   119 */   

   120    rule feedInput;

   121      let command <- server_stub.acceptRequest_SendUnprocessedStream();

   122      AudioProcessorControl ctrl = unpack(truncate(command.ctrl));

   123      if(ctrl == EndOfFile)

   124 	begin

   125 	  $display("lsp: PROCESSOR received EOF   ");

   126           core.sampleInput.put(tagged EndOfFile);

   127        end

   128      else 

   129 	begin

   130 	  $display("lsp: PROCESSOR received Data   ");

   131           core.sampleInput.put(tagged Sample unpack(truncate(command.sample)));

   132        end

   133    endrule     

   134 endmodule
author	rlm
date	Tue, 04 May 2010 19:53:09 -0400
parents	5a30f173bbac
children	16ba43f0a7c3