Mercurial > pygar
view modules/bluespec/Pygar/lab4/BRegFile.bsv @ 61:74d2fe78f36a pygar svn.62
[svn r62] synthesis boundaries
author | punk |
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date | Mon, 10 May 2010 20:31:25 -0400 |
parents | 6179c07c21d7 |
children | 90fa9b289aab |
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1 import RegFile::*;2 import RWire::*;3 import ProcTypes::*;5 `include "asim/provides/low_level_platform_interface.bsh"6 `include "asim/provides/soft_connections.bsh"7 `include "asim/provides/fpga_components.bsh"8 `include "asim/provides/common_services.bsh"10 //-----------------------------------------------------------11 // Register file module12 //-----------------------------------------------------------14 interface BRegFile #(type index_t, type data_t);15 method Action upd(index_t addr, data_t data);16 method data_t sub(index_t addr);17 endinterface20 (* doc = "synthesis attribute ram_style mkBRegFile distributed;" *)21 (* synthesize *)22 module mkBRegFile(RegFile#(index_t, data_t))23 provisos (Bits#(index_t, size_index),24 Bits#(data_t, size_data),25 Eq#(index_t),26 Bounded#(index_t) );28 LUTRAM#(index_t, data_t) rf <- mkLUTRAMU_RegFile();29 RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire();31 method Action upd (index_t r, data_t d);32 rf.upd(r,d);33 rw.wset(tuple2(r,d));34 endmethod36 method data_t sub (index_t r);37 case (rw.wget()) matches38 tagged Valid {.wr, .d} :39 return (wr == r) ? d : rf.sub(r);40 tagged Invalid : return rf.sub(r);41 endcase42 endmethod44 endmodule