Mercurial > pygar

     1 // The MIT License

     2 

     3 // Copyright (c) 2009 Massachusetts Institute of Technology

     4 

     5 // Permission is hereby granted, free of charge, to any person obtaining a copy

     6 // of this software and associated documentation files (the "Software"), to deal

     7 // in the Software without restriction, including without limitation the rights

     8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

     9 // copies of the Software, and to permit persons to whom the Software is

    10 // furnished to do so, subject to the following conditions:

    11 

    12 // The above copyright notice and this permission notice shall be included in

    13 // all copies or substantial portions of the Software.

    14 

    15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

    16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

    17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

    18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

    19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

    20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

    21 // THE SOFTWARE.

    22 

    23 import Connectable::*;

    24 import GetPut::*;

    25 import ClientServer::*;

    26 import FIFOF::*;

    27 import FIFO::*;

    28 

    29 // Local includes

    30 `include "asim/provides/processor_library.bsh"

    31 

    32 interface MemArb;

    33 

    34   interface Server#(MainMemReq,MainMemResp) cache0_server;

    35   interface Server#(MainMemReq,MainMemResp) cache1_server;

    36   interface Client#(MainMemReq,MainMemResp) mmem_client;

    37 

    38 endinterface

    39 

    40 typedef enum { REQ0, REQ1 } ReqPtr deriving(Eq,Bits);

    41 

    42 module mkMemArb( MemArb );

    43 

    44   //-----------------------------------------------------------

    45   // State

    46 

    47   FIFOF#(MainMemReq) req0Q  <- mkBFIFOF1();

    48   FIFO#(MainMemResp) resp0Q <- mkBFIFO1();

    49 

    50   FIFOF#(MainMemReq) req1Q  <- mkBFIFOF1();

    51   FIFO#(MainMemResp) resp1Q <- mkBFIFO1();

    52 

    53   FIFO#(MainMemReq)  mreqQ  <- mkBFIFO1();

    54   FIFO#(MainMemResp) mrespQ <- mkBFIFO1();

    55 

    56   Reg#(ReqPtr) nextReq <- mkReg(REQ0);

    57 

    58   //-----------------------------------------------------------

    59   // Some wires

    60 

    61   let req0avail = req0Q.notEmpty();

    62   let req1avail = req1Q.notEmpty();

    63   

    64   //-----------------------------------------------------------

    65   // Rules

    66 

    67   rule chooseReq0 ( req0avail && (!req1avail || (nextReq == REQ0)) );

    68     traceTiny("mkMemArb", "memArb req0",req0Q.first());

    69 

    70     // Rewrite tag field if this is a load ...

    71     MainMemReq mreq

    72      = case ( req0Q.first() ) matches

    73 	 tagged LoadReq  .ld : return LoadReq { tag:0, addr:ld.addr };

    74 	 tagged StoreReq .st : return req0Q.first();

    75        endcase;

    76 

    77     // Send out the request

    78     mreqQ.enq(mreq);

    79     nextReq <= REQ1;

    80     req0Q.deq();

    81 

    82   endrule

    83 

    84   rule chooseReq1 ( req1avail && (!req0avail || (nextReq == REQ1)) );

    85     traceTiny("mkMemArb", "memArb req1",req1Q.first);

    86 

    87     // Rewrite tag field if this is a load ...

    88     MainMemReq mreq 

    89      = case ( req1Q.first() ) matches

    90          tagged LoadReq  .ld : return LoadReq { tag:1, addr:ld.addr };

    91 	 tagged StoreReq .st : return req1Q.first();

    92        endcase;

    93 

    94     // Send out the request

    95     mreqQ.enq(mreq);

    96     nextReq <= REQ0;

    97     req1Q.deq();

    98 

    99   endrule

   100 

   101   rule returnResp;

   102     traceTiny("mkMemArb", "resp",mrespQ.first());

   103 

   104     // Use tag to figure out where to send response

   105     mrespQ.deq();

   106     let tag 

   107      = case ( mrespQ.first() ) matches

   108 	 tagged LoadResp  .ld : return ld.tag;

   109 	 tagged StoreResp .st : return st.tag;

   110        endcase;

   111      

   112     if ( tag == 0 ) 

   113       resp0Q.enq(mrespQ.first());                                    

   114     else

   115       resp1Q.enq(mrespQ.first());

   116 

   117   endrule

   118 

   119   //-----------------------------------------------------------

   120   // Methods

   121   

   122   interface Server cache0_server;

   123     interface Put request  = fifofToPut(req0Q);

   124     interface Get response = fifoToGet(resp0Q);

   125   endinterface

   126 

   127   interface Server cache1_server;

   128     interface Put request  = fifofToPut(req1Q);

   129     interface Get response = fifoToGet(resp1Q);

   130   endinterface

   131 

   132   interface Client mmem_client;

   133     interface Get request  = fifoToGet(mreqQ);

   134     interface Put response = fifoToPut(mrespQ);

   135   endinterface

   136 

   137 endmodule

   138 

   139
author	rlm
date	Fri, 23 Apr 2010 02:32:05 -0400
parents
children	3958de09a7c1