Mercurial > pygar
view modules/bluespec/Pygar/core/Core.bsv @ 8:74716e9a81cc pygar svn.9
[svn r9] Pygar now has the proper directory structure to play nicely with awb. Also, the apm file for audio-core willcompile successfully.
author | rlm |
---|---|
date | Fri, 23 Apr 2010 02:32:05 -0400 |
parents | |
children |
line wrap: on
line source
1 // The MIT License3 // Copyright (c) 2009 Massachusetts Institute of Technology5 // Permission is hereby granted, free of charge, to any person obtaining a copy6 // of this software and associated documentation files (the "Software"), to deal7 // in the Software without restriction, including without limitation the rights8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell9 // copies of the Software, and to permit persons to whom the Software is10 // furnished to do so, subject to the following conditions:12 // The above copyright notice and this permission notice shall be included in13 // all copies or substantial portions of the Software.15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN21 // THE SOFTWARE.23 import Connectable::*;24 import GetPut::*;25 import ClientServer::*;27 import DataCacheBlocking::*;28 import InstCacheBlocking::*;29 import Processor::*;30 import MemArb::*;31 import MemTypes::*;33 interface CoreStats;34 interface DCacheStats dcache;35 interface ICacheStats icache;36 interface ProcStats proc;37 endinterface39 interface Core;41 // Interface from core to main memory42 interface Client#(MainMemReq,MainMemResp) mmem_client;44 // Statistics45 interface CoreStats stats;47 // CPU to Host48 interface CPUToHost tohost;50 endinterface52 (* synthesize *)53 module mkCore(Core);55 // Instantiate the modules56 Proc proc <- mkProc();57 ICache#(InstReq,InstResp) icache <- mkInstCache();58 DCache#(DataReq,DataResp) dcache <- mkDataCache();59 MemArb marb <- mkMemArb();61 // Internal connections62 mkConnection( proc.statsEn_get, icache.statsEn_put );63 mkConnection( proc.statsEn_get, dcache.statsEn_put );64 mkConnection( proc.imem_client, icache.proc_server );65 mkConnection( proc.dmem_client, dcache.proc_server );66 mkConnection( icache.mmem_client, marb.cache0_server );67 mkConnection( dcache.mmem_client, marb.cache1_server );69 // Methods70 interface mmem_client = marb.mmem_client;72 interface CoreStats stats;73 interface dcache = dcache.stats;74 interface icache = icache.stats;75 interface proc = proc.stats;76 endinterface78 interface CPUToHost tohost = proc.tohost;80 endmodule