Mercurial > pygar
view modules/bluespec/Pygar/core/audioCorePipeline.bsv~ @ 13:6d461680c6d9 pygar svn.14
[svn r14] more stuff
author | punk |
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date | Tue, 27 Apr 2010 09:03:28 -0400 |
parents | |
children | a1833d9f6e3d |
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1 // The MIT License3 // Copyright (c) 2009 Massachusetts Institute of Technology5 // Permission is hereby granted, free of charge, to any person obtaining a copy6 // of this software and associated documentation files (the "Software"), to deal7 // in the Software without restriction, including without limitation the rights8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell9 // copies of the Software, and to permit persons to whom the Software is10 // furnished to do so, subject to the following conditions:12 // The above copyright notice and this permission notice shall be included in13 // all copies or substantial portions of the Software.15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN21 // THE SOFTWARE.23 // Author: Kermin Fleming kfleming@mit.edu25 import Connectable::*;26 import GetPut::*;27 import ClientServer::*;28 import FIFO::*;30 //AWB includes31 `include "asim/provides/low_level_platform_interface.bsh"32 `include "asim/provides/soft_connections.bsh"33 `include "asim/provides/common_services.bsh"35 //Local includes36 `include "asim/provides/audio_processor_types.bsh" //provides Audio Pipeline interface37 `include "asim/provides/core.bsh"39 `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"40 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"42 module [CONNECTED_MODULE] mkConnectedApplication ();43 Core core <- mkCore;44 Reg#(int) cycle <- mkReg(0);46 //External memory47 // I'm not comfortable assuming that the memory subsystem is in order48 // So I'll insert a completion buffer here.49 ClientStub_PROCESSORSYSTEMRRR client_stub <- mkClientStub_PROCESSORSYSTEMRRR();50 // Make this big enough so that several outstanding requests may be supported51 FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);53 // this is for the tracing54 rule printCycles;55 cycle <= cycle+1;56 $fdisplay(stderr, " => Cycle = %d", cycle);57 endrule59 rule sendMemReq;60 let coreReq <- core.mmem_client.request.get;61 case (coreReq) matches62 tagged LoadReq .load: begin63 //Allocate ROB space64 client_stub.makeRequest_MemoryRequestLoad(load.addr);65 tags.enq(load.tag);66 end67 tagged StoreReq .store: begin68 client_stub.makeRequest_MemoryRequestStore(store.addr,store.data);69 end70 endcase71 endrule73 rule receiveMemResp;74 let memResp <- client_stub.getResponse_MemoryRequestLoad();75 tags.deq;76 core.mmem_client.response.put(tagged LoadResp {data:memResp,77 tag: tags.first});78 endrule80 // this isn't particularly correct as it doesn't actually connect the processor interfaces, but this should allow me to verify the data path before fully blending the two items together.82 rule feedOutput;83 let pipelineData <- core.sampleOutput.get();84 AudioProcessorControl endOfFileTag = EndOfFile;85 AudioProcessorControl sampleTag = Data;87 case (pipelineData) matches88 tagged EndOfFile: client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?);89 tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)),90 zeroExtend(pack(sample)));91 endcase92 endrule94 endmodule