Mercurial > pygar

     1 // The MIT License

     2 

     3 // Copyright (c) 2009 Massachusetts Institute of Technology

     4 

     5 // Permission is hereby granted, free of charge, to any person obtaining a copy

     6 // of this software and associated documentation files (the "Software"), to deal

     7 // in the Software without restriction, including without limitation the rights

     8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

     9 // copies of the Software, and to permit persons to whom the Software is

    10 // furnished to do so, subject to the following conditions:

    11 

    12 // The above copyright notice and this permission notice shall be included in

    13 // all copies or substantial portions of the Software.

    14 

    15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

    16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

    17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

    18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

    19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

    20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

    21 // THE SOFTWARE.

    22 

    23 import Connectable::*;

    24 import GetPut::*;

    25 import ClientServer::*;

    26 import Processor::*;

    27 import MemArb::*;

    28 import MemTypes::*;

    29 

    30 //AWB includes

    31 `include "asim/provides/low_level_platform_interface.bsh"

    32 `include "asim/provides/soft_connections.bsh"

    33 `include "asim/provides/common_services.bsh"

    34 

    35 // Local includes

    36 `include "asim/provides/processor_library.bsh"

    37 `include "asim/provides/mem_arb.bsh"

    38 `include "asim/provides/instruction_cache.bsh"

    39 `include "asim/provides/data_cache.bsh"

    40 `include "asim/provides/processor.bsh"

    41 

    42 interface Core;

    43 

    44   // Interface from core to main memory

    45    interface Client#(MainMemReq,MainMemResp) mmem_client;

    46 

    47    interface CPUToHost tohost;

    48 	 

    49    interface AudioIn audio;

    50 

    51 endinterface

    52 

    53 interface AudioIn;

    54  //     interface Put#(AudioProcessorUnit) sampleInput;

    55       interface Get#(AudioProcessorUnit) sampleOutput;

    56 endinterface      

    57 

    58 module   [CONNECTED_MODULE]  mkCore( Core );

    59 

    60   // Instantiate the modules

    61 

    62   Proc proc <- mkProc();

    63   ICache#(InstReq,InstResp) icache <- mkInstCache();

    64   DCache#(DataReq,DataResp) dcache <- mkDataCache();

    65   MemArb marb <- mkMemArb();

    66 

    67   // Internal connections

    68 

    69   mkConnection( proc.statsEn_get,   icache.statsEn_put );

    70   mkConnection( proc.statsEn_get,   dcache.statsEn_put );

    71   mkConnection( proc.imem_client,   icache.proc_server );

    72   mkConnection( proc.dmem_client,   dcache.proc_server );

    73   mkConnection( icache.mmem_client, marb.cache0_server );

    74   mkConnection( dcache.mmem_client, marb.cache1_server );

    75 

    76   // Methods

    77 

    78    interface mmem_client = marb.mmem_client;

    79 

    80    interface CPUToHost tohost = proc.tohost;

    81 

    82    interface AudioIn audio = proc.audioIn;

    83 

    84 endmodule
author	punk
date	Tue, 27 Apr 2010 09:03:28 -0400
parents
children	a1833d9f6e3d