Mercurial > pygar

     1 // The MIT License

     2 

     3 // Copyright (c) 2009 Massachusetts Institute of Technology

     4 

     5 // Permission is hereby granted, free of charge, to any person obtaining a copy

     6 // of this software and associated documentation files (the "Software"), to deal

     7 // in the Software without restriction, including without limitation the rights

     8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

     9 // copies of the Software, and to permit persons to whom the Software is

    10 // furnished to do so, subject to the following conditions:

    11 

    12 // The above copyright notice and this permission notice shall be included in

    13 // all copies or substantial portions of the Software.

    14 

    15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

    16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

    17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

    18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

    19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

    20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

    21 // THE SOFTWARE.

    22 

    23 import Connectable::*;

    24 import GetPut::*;

    25 import ClientServer::*;

    26 import FIFOF::*;

    27 import FIFO::*;

    28 import Trace::*;

    29 

    30 // Local includes

    31 `include "asim/provides/processor_library.bsh"

    32 

    33 interface MemArb;

    34 

    35   interface Server#(MainMemReq,MainMemResp) cache0_server;

    36   interface Server#(MainMemReq,MainMemResp) cache1_server;

    37   interface Client#(MainMemReq,MainMemResp) mmem_client;

    38 

    39 endinterface

    40 

    41 typedef enum { REQ0, REQ1 } ReqPtr deriving(Eq,Bits);

    42 

    43 module mkMemArb( MemArb );

    44 

    45   //-----------------------------------------------------------

    46   // State

    47 

    48   FIFOF#(MainMemReq) req0Q  <- mkBFIFOF1();

    49   FIFO#(MainMemResp) resp0Q <- mkBFIFO1();

    50 

    51   FIFOF#(MainMemReq) req1Q  <- mkBFIFOF1();

    52   FIFO#(MainMemResp) resp1Q <- mkBFIFO1();

    53 

    54   FIFO#(MainMemReq)  mreqQ  <- mkBFIFO1();

    55   FIFO#(MainMemResp) mrespQ <- mkBFIFO1();

    56 

    57   Reg#(ReqPtr) nextReq <- mkReg(REQ0);

    58 

    59   //-----------------------------------------------------------

    60   // Some wires

    61 

    62   let req0avail = req0Q.notEmpty();

    63   let req1avail = req1Q.notEmpty();

    64   

    65   //-----------------------------------------------------------

    66   // Rules

    67 

    68   rule chooseReq0 ( req0avail && (!req1avail || (nextReq == REQ0)) );

    69     traceTiny("mkMemArb", "memArb req0",req0Q.first());

    70 

    71     // Rewrite tag field if this is a load ...

    72     MainMemReq mreq

    73      = case ( req0Q.first() ) matches

    74 	 tagged LoadReq  .ld : return LoadReq { tag:0, addr:ld.addr };

    75 	 tagged StoreReq .st : return req0Q.first();

    76        endcase;

    77 

    78     // Send out the request

    79     mreqQ.enq(mreq);

    80     nextReq <= REQ1;

    81     req0Q.deq();

    82 

    83   endrule

    84 

    85   rule chooseReq1 ( req1avail && (!req0avail || (nextReq == REQ1)) );

    86     traceTiny("mkMemArb", "memArb req1",req1Q.first);

    87 

    88     // Rewrite tag field if this is a load ...

    89     MainMemReq mreq 

    90      = case ( req1Q.first() ) matches

    91          tagged LoadReq  .ld : return LoadReq { tag:1, addr:ld.addr };

    92 	 tagged StoreReq .st : return req1Q.first();

    93        endcase;

    94 

    95     // Send out the request

    96     mreqQ.enq(mreq);

    97     nextReq <= REQ0;

    98     req1Q.deq();

    99 

   100   endrule

   101 

   102   rule returnResp;

   103     traceTiny("mkMemArb", "resp",mrespQ.first());

   104 

   105     // Use tag to figure out where to send response

   106     mrespQ.deq();

   107     let tag 

   108      = case ( mrespQ.first() ) matches

   109 	 tagged LoadResp  .ld : return ld.tag;

   110 	 tagged StoreResp .st : return st.tag;

   111        endcase;

   112      

   113     if ( tag == 0 ) 

   114       resp0Q.enq(mrespQ.first());                                    

   115     else

   116       resp1Q.enq(mrespQ.first());

   117 

   118   endrule

   119 

   120   //-----------------------------------------------------------

   121   // Methods

   122   

   123   interface Server cache0_server;

   124     interface Put request  = fifofToPut(req0Q);

   125     interface Get response = fifoToGet(resp0Q);

   126   endinterface

   127 

   128   interface Server cache1_server;

   129     interface Put request  = fifofToPut(req1Q);

   130     interface Get response = fifoToGet(resp1Q);

   131   endinterface

   132 

   133   interface Client mmem_client;

   134     interface Get request  = fifoToGet(mreqQ);

   135     interface Put response = fifoToPut(mrespQ);

   136   endinterface

   137 

   138 endmodule

   139 

   140
author	punk
date	Tue, 11 May 2010 21:02:59 -0400
parents	3958de09a7c1
children