Mercurial > pygar
view modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv @ 66:6bd9397cd591 pygar svn.67
[svn r67] added a couple sound files
author | punk |
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date | Tue, 11 May 2010 21:02:59 -0400 |
parents | 1d5cbb5343d2 |
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1 // The MIT License3 // Copyright (c) 2009 Massachusetts Institute of Technology5 // Permission is hereby granted, free of charge, to any person obtaining a copy6 // of this software and associated documentation files (the "Software"), to deal7 // in the Software without restriction, including without limitation the rights8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell9 // copies of the Software, and to permit persons to whom the Software is10 // furnished to do so, subject to the following conditions:12 // The above copyright notice and this permission notice shall be included in13 // all copies or substantial portions of the Software.15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN21 // THE SOFTWARE.23 // Local includes24 `include "asim/provides/low_level_platform_interface.bsh"25 `include "asim/provides/soft_connections.bsh"26 `include "asim/provides/processor_library.bsh"27 `include "asim/provides/fpga_components.bsh"28 `include "asim/provides/common_services.bsh"30 import Connectable::*;31 import GetPut::*;32 import ClientServer::*;33 import RegFile::*;34 import FIFO::*;35 import FIFOF::*;36 import Trace::*;38 interface DCache#( type req_t, type resp_t );40 // Interface from processor to cache41 interface Server#(req_t,resp_t) proc_server;43 // Interface from cache to main memory44 interface Client#(MainMemReq,MainMemResp) mmem_client;46 // Interface for enabling/disabling statistics47 interface Put#(Bool) statsEn_put;49 endinterface52 //----------------------------------------------------------------------53 // Cache Types54 //----------------------------------------------------------------------56 typedef 10 CacheLineIndexSz;57 typedef 20 CacheLineTagSz;58 typedef 32 CacheLineSz;60 typedef Bit#(CacheLineIndexSz) CacheLineIndex;61 typedef Bit#(CacheLineTagSz) CacheLineTag;62 typedef Bit#(CacheLineSz) CacheLine;64 typedef enum65 {66 Init,67 Access,68 RefillReq,69 RefillResp70 }71 CacheStage72 deriving (Eq,Bits);74 //----------------------------------------------------------------------75 // Helper functions76 //----------------------------------------------------------------------78 function Bit#(AddrSz) getAddr( DataReq req );80 Bit#(AddrSz) addr = ?;81 case ( req ) matches82 tagged LoadReq .ld : addr = ld.addr;83 tagged StoreReq .st : addr = st.addr;84 endcase86 return addr;88 endfunction90 function CacheLineIndex getCacheLineIndex( DataReq req );91 Bit#(AddrSz) addr = getAddr(req);92 Bit#(CacheLineIndexSz) index = truncate( addr >> 2 );93 return index;94 endfunction96 function CacheLineTag getCacheLineTag( DataReq req );97 Bit#(AddrSz) addr = getAddr(req);98 Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 );99 return tag;100 endfunction102 function Bit#(AddrSz) getCacheLineAddr( DataReq req );103 Bit#(AddrSz) addr = getAddr(req);104 return ((addr >> 2) << 2);105 endfunction107 //----------------------------------------------------------------------108 // Main module109 //----------------------------------------------------------------------111 (* doc = "synthesis attribute ram_style mkDataCache distributed;" *)112 (* synthesize *)113 module mkDataCache( DCache#(DataReq,DataResp) );115 //-----------------------------------------------------------116 // State118 Reg#(CacheStage) stage <- mkReg(Init);120 LUTRAM#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkLUTRAMU_RegFile();121 LUTRAM#(CacheLineIndex,CacheLine) cacheDataRam <- mkLUTRAMU_RegFile();123 FIFO#(DataReq) reqQ <- mkFIFO();124 FIFOF#(DataResp) respQ <- mkBFIFOF1();126 FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1();127 FIFO#(MainMemResp) mainMemRespQ <- mkFIFO();129 Reg#(CacheLineIndex) initCounter <- mkReg(1);131 // Statistics state133 Reg#(Bool) statsEn <- mkReg(False);134 //rlm:135 //STAT num_accesses <- mkStatCounter(`STATS_DATA_CACHE_NUM_ACCESSES);136 //STAT num_misses <- mkStatCounter(`STATS_DATA_CACHE_NUM_MISSES);137 //STAT num_writebacks <- mkStatCounter(`STATS_DATA_CACHE_NUM_WRITEBACKS);139 //-----------------------------------------------------------140 // Name some wires142 let req = reqQ.first();143 let reqIndex = getCacheLineIndex(req);144 let reqTag = getCacheLineTag(req);145 let reqCacheLineAddr = getCacheLineAddr(req);147 //-----------------------------------------------------------148 // Initialize150 rule init ( stage == Init );151 traceTiny("mkDataCacheBlocking", "stage","i");152 initCounter <= initCounter + 1;153 cacheTagRam.upd(initCounter,Invalid);154 if ( initCounter == 0 )155 stage <= Access;156 endrule158 //-----------------------------------------------------------159 // Access cache rule161 rule access ( (stage == Access) && respQ.notFull() );163 // Statistics164 //rlm:165 //if ( statsEn )166 // num_accesses.incr();169 // Get the corresponding tag from the rams171 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);173 // Handle cache hits ...175 if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) )176 begin177 traceTiny("mkDataCacheBlocking", "hitMiss","h");178 reqQ.deq();180 case ( req ) matches182 tagged LoadReq .ld :183 respQ.enq( LoadResp { tag: ld.tag, data: cacheDataRam.sub(reqIndex) } );185 tagged StoreReq .st :186 begin187 respQ.enq( StoreResp { tag : st.tag } );188 cacheDataRam.upd(reqIndex,st.data);189 end191 endcase193 end195 // Handle cache misses ...197 else198 begin199 traceTiny("mkDataCacheBlocking", "hitMiss","m");200 //rlm:201 //if ( statsEn )202 // num_misses.incr();204 // Currently we don't use dirty bits so we always writeback the data if it is valid206 if ( isValid(cacheLineTag) )207 begin208 //rlm:209 // if ( statsEn )210 // num_writebacks.incr();212 MainMemReq wbReq213 = StoreReq { tag : 0,214 addr : { unJust(cacheLineTag), reqIndex, 2'b0 },215 data : cacheDataRam.sub(reqIndex) };217 mainMemReqQ.enq(wbReq);218 stage <= RefillReq;219 end221 // Otherwise we can issue the refill request now223 else224 begin225 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } );226 stage <= RefillResp;227 end229 end231 endrule233 //-----------------------------------------------------------234 // Refill request rule236 rule refillReq ( stage == RefillReq );237 traceTiny("mkDataCacheBlocking", "stage","r");238 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } );239 stage <= RefillResp;240 endrule242 //-----------------------------------------------------------243 // Refill response rule245 rule refillResp ( stage == RefillResp );246 traceTiny("mkDataCacheBlocking", "stage","R");247 traceTiny("mkDataCacheBlocking", "refill",mainMemRespQ.first());249 // Write the new data into the cache and update the tag251 mainMemRespQ.deq();252 case ( mainMemRespQ.first() ) matches254 tagged LoadResp .ld :255 begin256 cacheTagRam.upd(reqIndex,Valid(reqTag));257 cacheDataRam.upd(reqIndex,ld.data);258 end260 tagged StoreResp .st :261 noAction;263 endcase265 stage <= Access;266 endrule268 //-----------------------------------------------------------269 // Methods271 interface Client mmem_client;272 interface Get request = fifoToGet(mainMemReqQ);273 interface Put response = fifoToPut(mainMemRespQ);274 endinterface276 interface Server proc_server;277 interface Put request = tracePut("mkDataCacheBlocking", "reqTiny",fifoToPut(reqQ));278 interface Get response = traceGet("mkDataCacheBlocking", "respTiny",fifofToGet(respQ));279 endinterface281 interface Put statsEn_put = regToPut(statsEn);283 endmodule