Mercurial > pygar

     1 /// The MIT License

     2 

     3 // Copyright (c) 2009 Massachusetts Institute of Technology

     4 

     5 // Permission is hereby granted, free of charge, to any person obtaining a copy

     6 // of this software and associated documentation files (the "Software"), to deal

     7 // in the Software without restriction, including without limitation the rights

     8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

     9 // copies of the Software, and to permit persons to whom the Software is

    10 // furnished to do so, subject to the following conditions:

    11 

    12 // The above copyright notice and this permission notice shall be included in

    13 // all copies or substantial portions of the Software.

    14 

    15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

    16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

    17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

    18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

    19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

    20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

    21 // THE SOFTWARE.

    22 

    23 

    24 import Connectable::*;

    25 import GetPut::*;

    26 import ClientServer::*;

    27 import RegFile::*;

    28 

    29 import FIFO::*;

    30 import FIFOF::*;

    31 import SFIFO::*;

    32 import RWire::*;

    33 

    34 import Trace::*;

    35 import BFIFO::*;

    36 import MemTypes::*;

    37 import ProcTypes::*;

    38 import BRegFile::*;

    39 import BranchPred::*;

    40 //import PathTypes::*;  This is only there to force the debugging

    41 

    42 //AWB includes

    43 `include "asim/provides/low_level_platform_interface.bsh"

    44 `include "asim/provides/soft_connections.bsh"

    45 `include "asim/provides/common_services.bsh"

    46 

    47 // Local includes

    48 //`include "asim/provides/processor_library.bsh" (included above directly)

    49 

    50 `include "asim/provides/common_services.bsh"

    51 `include "asim/dict/STATS_PROCESSOR.bsh"

    52 `include "asim/provides/processor_library.bsh"

    53 

    54 // Local includes. Look for the correspondingly named .awb files

    55 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/

    56 // to find the actual Bluespec files which are used to generate

    57 // these includes.  These files are specific to this audio processing

    58 // pipeline

    59 

    60 `include "asim/provides/audio_pipe_types.bsh"

    61 

    62 //interface CPUToHost;

    63 //  method Bit#(32) cpuToHost(int req);

    64 //endinterface

    65 

    66 interface Proc;

    67 

    68   // Interface from processor to caches

    69   interface Client#(DataReq,DataResp) dmem_client;

    70   interface Client#(InstReq,InstResp) imem_client;

    71 

    72   // Interface for enabling/disabling statistics on the rest of the core

    73   interface Get#(Bool) statsEn_get;

    74 

    75 //  // Interface to host

    76 //  interface CPUToHost tohost;

    77 

    78   // Interface to Audio Pipeline

    79   interface Get#(AudioProcessorUnit) sampleOutput;

    80   interface Put#(AudioProcessorUnit) sampleInput;

    81 	

    82 endinterface

    83 

    84 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);

    85 

    86 //-----------------------------------------------------------

    87 // Register file module

    88 //-----------------------------------------------------------

    89 

    90 interface BRFile;

    91    method Action   wr( Rindx rindx, Bit#(32) data );

    92    method Bit#(32) rd1( Rindx rindx );

    93    method Bit#(32) rd2( Rindx rindx );

    94 endinterface

    95 

    96 module mkBRFile( BRFile );

    97    

    98    RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();

    99    

   100    method Action wr( Rindx rindx, Bit#(32) data );

   101       rfile.upd( rindx, data );

   102    endmethod

   103    

   104    method Bit#(32) rd1( Rindx rindx );

   105       return ( rindx == 0 ) ? 0 : rfile.sub(rindx);

   106    endmethod

   107    

   108    method Bit#(32) rd2( Rindx rindx );

   109       return ( rindx == 0 ) ? 0 : rfile.sub(rindx);

   110    endmethod

   111 

   112 endmodule

   113 

   114 //-----------------------------------------------------------

   115 // Helper functions

   116 //-----------------------------------------------------------

   117 

   118 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );

   119    return zeroExtend( pack( signedLT(val1,val2) ) );

   120 endfunction

   121 

   122 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );

   123    return zeroExtend( pack( val1 < val2 ) );

   124 endfunction

   125 

   126 function Bit#(32) rshft( Bit#(32) val );

   127    return zeroExtend(val[4:0]);

   128 endfunction

   129 

   130 

   131 //-----------------------------------------------------------

   132 // Find funct for wbQ

   133 //-----------------------------------------------------------

   134 function Bool findwbf(Rindx fVal, WBResult cmpVal);

   135   case (cmpVal) matches   

   136      tagged WB_ALU  {data:.res, dest:.rd} :

   137 	return (fVal == rd);

   138      tagged WB_Load .rd  :

   139 	return (fVal == rd);

   140      tagged WB_Store .st :

   141 	return False;

   142      tagged WB_Host .x   :

   143 	return False;

   144   endcase

   145 endfunction

   146 

   147      

   148 //-----------------------------------------------------------

   149 // Stall funct for wbQ

   150 //-----------------------------------------------------------

   151 function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);

   152    case (inst) matches

   153       	 // -- Memory Ops ------------------------------------------------      

   154       tagged LW .it :

   155 	 return f.find(it.rbase);

   156       tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :

   157 	 return (f.find(addr) ||  f.find2(dreg));

   158 

   159 	 // -- Simple Ops ------------------------------------------------      

   160       tagged ADDIU .it : return f.find(it.rsrc);

   161       tagged SLTI  .it : return f.find(it.rsrc);

   162       tagged SLTIU .it : return f.find(it.rsrc);

   163       tagged ANDI  .it : return f.find(it.rsrc);

   164       tagged ORI   .it : return f.find(it.rsrc);

   165       tagged XORI  .it : return f.find(it.rsrc);

   166       

   167       tagged LUI   .it : return f.find(it.rdst);  //this rds/wrs itself

   168       tagged SLL   .it : return f.find(it.rsrc);

   169       tagged SRL   .it : return f.find(it.rsrc);

   170       tagged SRA   .it : return f.find(it.rsrc);

   171       tagged SLLV  .it : return (f.find(it.rsrc) || f.find(it.rshamt));

   172       tagged SRLV  .it : return (f.find(it.rsrc) || f.find(it.rshamt));

   173       tagged SRAV  .it : return (f.find(it.rsrc) || f.find(it.rshamt));

   174       tagged ADDU  .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

   175       tagged SUBU  .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

   176       tagged AND   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

   177       tagged OR    .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

   178       tagged XOR   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

   179       tagged NOR   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

   180       tagged SLT   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

   181       tagged SLTU  .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

   182    

   183 

   184       // -- Branches --------------------------------------------------

   185     

   186       tagged BLEZ  .it : return (f.find(it.rsrc));

   187       tagged BGTZ  .it : return (f.find(it.rsrc));

   188       tagged BLTZ  .it : return (f.find(it.rsrc));

   189       tagged BGEZ  .it : return (f.find(it.rsrc));

   190       tagged BEQ   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

   191       tagged BNE   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));

   192       

   193       // -- Jumps -----------------------------------------------------

   194       

   195       tagged J     .it : return False;

   196       tagged JR    .it : return f.find(it.rsrc);

   197       tagged JALR  .it : return f.find(it.rsrc);

   198       tagged JAL   .it : return False;

   199       

   200       // -- Cop0 ------------------------------------------------------

   201       

   202       tagged MTC0  .it : return f.find(it.rsrc);      

   203       tagged MFC0  .it : return False; 

   204 

   205       // -- Illegal ---------------------------------------------------

   206 

   207       default : return False;

   208 

   209     endcase

   210 endfunction

   211 //-----------------------------------------------------------

   212 // Reference processor

   213 //-----------------------------------------------------------

   214 

   215 

   216 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)

   217 //(* synthesize *)

   218 

   219 module  [CONNECTED_MODULE] mkProc( Proc );

   220 

   221    //-----------------------------------------------------------

   222    // State

   223 

   224    // Standard processor state

   225    

   226    Reg#(Addr)  pc    <- mkReg(32'h00001000);

   227    Reg#(Epoch) epoch <- mkReg(0);

   228    Reg#(Stage) stage <- mkReg(PCgen);

   229    BRFile      rf    <- mkBRFile;

   230 

   231    // Branch Prediction

   232    BranchPred               bp <- mkBranchPred();

   233    FIFO#(PCStat)        execpc <- mkLFIFO();

   234    

   235    // Pipelines

   236    FIFO#(PCStat)           pcQ <-mkSizedFIFO(3);

   237    SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);

   238 

   239    // NEED TO ADD CAPABILITY FOR RESET (should be able to just say if I get valid in and these are flagged, clear them.

   240    Reg#(Bit#(32)) cp0_tohost   <- mkReg(0);

   241    Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);

   242    Reg#(Bool)     cp0_statsEn  <- mkReg(False);

   243    Reg#(Bool)     cp0_audioEOF <- mkReg(False);  // Register to let code that EOF is reached

   244    Reg#(Bool)     cp0_progComp <- mkReg(False);  // Register to let processor know that the program is complete (as this terminates)

   245     

   246    // Memory request/response state

   247    

   248    FIFO#(InstReq)  instReqQ    <- mkBFIFO1();

   249    FIFO#(InstResp) instRespQ   <- mkFIFO();

   250 

   251    FIFO#(DataReq)  dataReqQ    <- mkBFIFO1();

   252    FIFO#(DataResp) dataRespQ   <- mkFIFO();

   253 

   254    // Audio I/O

   255    FIFO#(AudioProcessorUnit) inAudioFifo <- mkSizedFIFO(512);

   256    FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;

   257 

   258 

   259    // Statistics state (2010)

   260    //   Reg#(Stat) num_cycles <- mkReg(0);

   261    //   Reg#(Stat) num_inst <- mkReg(0);

   262 

   263    //Or:

   264    // Statistics state

   265   

   266    //rlm: removing these to avoid their broken stupidness.

   267    //STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);

   268    //STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);

   269 

   270    //-----------------------------------------------------------

   271    // Rules

   272 

   273    (* descending_urgency = "exec, pcgen" *)

   274    rule pcgen; //( stage == PCgen );

   275       let pc_plus4 = pc + 4;

   276 

   277       traceTiny("mkProc", "pc",pc);

   278       traceTiny("mkProc", "pcgen","P");

   279       instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );

   280       

   281       let next_pc = bp.get(pc);

   282       if (next_pc matches tagged Valid .npc) 

   283 	begin

   284 	   pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});

   285 	   pc <= npc;

   286 	end

   287      else

   288 	 begin

   289 	   pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});

   290 	   pc <= pc_plus4;

   291 	 end

   292       

   293    endrule

   294 

   295    rule discard (instRespQ.first() matches tagged LoadResp .ld

   296 					      &&& ld.tag != epoch);

   297       traceTiny("mkProc", "stage", "D");

   298       instRespQ.deq();

   299    endrule

   300 

   301    (* conflict_free = "exec, writeback" *)		      

   302    rule exec (instRespQ.first() matches tagged LoadResp.ld

   303 	      &&& (ld.tag == epoch)

   304 	      &&& unpack(ld.data) matches .inst

   305               &&& !stall(inst, wbQ));

   306 

   307       // Some abbreviations

   308       let sext = signExtend;

   309       let zext = zeroExtend;

   310       let sra  = signedShiftRight;

   311       

   312       // Get the instruction

   313       

   314       instRespQ.deq();

   315       Instr inst 

   316       = case ( instRespQ.first() ) matches

   317 	   tagged LoadResp  .ld : return unpack(ld.data);

   318 	   tagged StoreResp .st : return ?;

   319 	endcase;

   320 

   321       // Get the PC info

   322       let instrpc = pcQ.first().qpc;

   323       let pc_plus4 = instrpc + 4;

   324       

   325       Bool branchTaken = False;

   326       Addr newPC = pc_plus4;

   327 

   328       // Tracing

   329       traceTiny("mkProc", "exec","X");

   330       traceTiny("mkProc", "exInstTiny",inst);

   331       traceFull("mkProc", "exInstFull",inst);

   332 

   333       case ( inst ) matches

   334 

   335 	 // -- Memory Ops ------------------------------------------------      

   336 

   337 	 tagged LW .it : 

   338 	    begin

   339                Addr addr = rf.rd1(it.rbase) + sext(it.offset);

   340                dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );

   341                wbQ.enq(tagged WB_Load it.rdst);

   342 	    end

   343 

   344 	 tagged SW .it : 

   345 	    begin

   346                Addr addr = rf.rd1(it.rbase) + sext(it.offset);

   347                dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );

   348                wbQ.enq(tagged WB_Store);

   349 	    end

   350 

   351 	 // -- Simple Ops ------------------------------------------------      

   352 

   353 	 tagged ADDIU .it : 

   354 	    begin

   355 	       Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);

   356 	       wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});

   357 	    end

   358 	 tagged SLTI  .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});

   359 	 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });

   360 	 tagged ANDI  .it : 

   361 	    begin

   362 	       Bit#(32) zext_it_imm = zext(it.imm);

   363 	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );

   364 	    end

   365 	 tagged ORI   .it : 

   366 	    begin

   367 	       Bit#(32) zext_it_imm = zext(it.imm);

   368 	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} );

   369 	    end

   370 	 tagged XORI  .it : 

   371 	    begin

   372 	       Bit#(32) zext_it_imm = zext(it.imm);

   373 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});

   374 	    end

   375 	 tagged LUI   .it : 

   376 	    begin

   377 	       Bit#(32) zext_it_imm = zext(it.imm);

   378 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });

   379 	    end

   380 	 

   381 	 tagged SLL   .it : 

   382 	    begin

   383 	       Bit#(32) zext_it_shamt = zext(it.shamt);

   384 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );

   385 	    end

   386 	 tagged SRL   .it : 

   387 	    begin

   388 	       Bit#(32) zext_it_shamt = zext(it.shamt);

   389 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});

   390 	    end

   391 	 tagged SRA   .it : 

   392 	    begin

   393 	       Bit#(32) zext_it_shamt = zext(it.shamt);

   394 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});

   395 	    end

   396 	 tagged SLLV  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});

   397 	 tagged SRLV  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );

   398 	 tagged SRAV  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });

   399 	 tagged ADDU  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );

   400 	 tagged SUBU  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );

   401 	 tagged AND   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );

   402 	 tagged OR    .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} );

   403 	 tagged XOR   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );

   404 	 tagged NOR   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} );

   405 	 tagged SLT   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });

   406 	 tagged SLTU  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });

   407 

   408 	 // -- Branches --------------------------------------------------

   409 

   410 	 tagged BLEZ  .it : 

   411             if ( signedLE( rf.rd1(it.rsrc), 0 ) )

   412 	       begin

   413 		  newPC = pc_plus4 + (sext(it.offset) << 2);

   414 		  branchTaken = True;

   415 	       end

   416 

   417 	 tagged BGTZ  .it : 

   418             if ( signedGT( rf.rd1(it.rsrc), 0 ) ) 

   419                begin 

   420 		  newPC = pc_plus4 + (sext(it.offset) << 2);

   421 		  branchTaken = True;

   422 	       end

   423 

   424 	 tagged BLTZ  .it : 

   425             if ( signedLT( rf.rd1(it.rsrc), 0 ) )

   426                begin 

   427 		  newPC = pc_plus4 + (sext(it.offset) << 2);

   428 		  branchTaken = True;

   429 	       end

   430 		  

   431 	 tagged BGEZ  .it : 

   432             if ( signedGE( rf.rd1(it.rsrc), 0 ) )

   433                begin 

   434 		  newPC = pc_plus4 + (sext(it.offset) << 2);		  

   435 		  branchTaken = True;

   436 	       end

   437 

   438       tagged BEQ   .it : 

   439         if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )

   440           begin 

   441 	     newPC = pc_plus4 + (sext(it.offset) << 2);

   442 	     branchTaken = True;

   443 	  end

   444 

   445       tagged BNE   .it : 

   446         if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )

   447           begin 

   448 	     newPC = pc_plus4 + (sext(it.offset) << 2);

   449 	     branchTaken = True;

   450 	  end

   451 

   452       // -- Jumps -----------------------------------------------------

   453       

   454       tagged J     .it : 

   455         begin 

   456 	   newPC = { pc_plus4[31:28], it.target, 2'b0 };

   457 	   branchTaken = True;

   458 	end

   459       

   460       tagged JR    .it : 

   461         begin

   462 	   newPC = rf.rd1(it.rsrc);

   463 	   branchTaken = True;

   464 	end

   465 

   466       tagged JAL   .it : 

   467        begin

   468           wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });

   469           newPC = { pc_plus4[31:28], it.target, 2'b0 };		  

   470 	  branchTaken = True;

   471        end

   472 

   473       tagged JALR  .it : 

   474        begin

   475           wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });

   476           newPC = rf.rd1(it.rsrc);

   477 	  branchTaken = True;

   478        end

   479 

   480       // -- Cop0 ------------------------------------------------------

   481       

   482       tagged MTC0  .it : //Recieve things from host computer

   483 	 begin

   484 //	    $display( " PROCESSOR MTC0 call\n");

   485             case ( it.cop0dst )

   486 	       5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));

   487 	       5'd21 : cp0_tohost  <= truncate(rf.rd1(it.rsrc));

   488 	       5'd26 : cp0_progComp <= unpack(truncate(rf.rd1(it.rsrc))); //states audio program completed and termination okay

   489  	       5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(rf.rd1(it.rsrc))));  //Bit size is 16 not 32 

   490 	       default :

   491 	       $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );

   492 	    endcase

   493 	    wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.

   494 	 end

   495 

   496 //this is host stuff?

   497       tagged MFC0  .it :  //Things out

   498 	 begin

   499             case ( it.cop0src )

   500 	    // not actually an ALU instruction but don't have the format otherwise

   501                5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });

   502                5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });

   503                5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost   });

   504 	       5'd25 : begin

   505 //			  $display( "**** EOF Requested\n ");

   506 			  wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_audioEOF)) });  // Reading clears bit

   507 			  cp0_audioEOF <= False;

   508 		       end

   509 	       5'd28 : begin

   510 //			  $display( "***** Reqesting Sample \n");

   511 			  let sample = inAudioFifo.first();        // is this going to cause perf. delay?

   512 			  if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF  

   513 	     		     wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) });  // do I need pack?

   514 			  else $display ( "Audio File EOF Reached.  Invalid sample request.");

   515 			  inAudioFifo.deq();

   516 		       end

   517               default : 

   518                 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );

   519             endcase

   520 	end

   521 

   522       // -- Illegal ---------------------------------------------------

   523 

   524       default : 

   525         $display( " RTL-ERROR : %m : Illegal instruction !" );

   526 

   527     endcase

   528 

   529 //evaluate branch prediction

   530      Addr ppc = pcQ.first().qnxtpc; //predicted branch

   531      if (ppc != newPC) //prediction wrong

   532        begin

   533 	  epoch <= pcQ.first().qepoch + 1;

   534 	  bp.upd(instrpc, newPC); //update branch predictor

   535 	  pcQ.clear();

   536 	  pc <= newPC;

   537        end

   538      else

   539 	pcQ.deq();

   540    //rlm: removing

   541    // if ( cp0_statsEn )

   542    //   num_inst.incr();

   543 

   544   endrule

   545 

   546   rule writeback; // ( stage == Writeback );

   547      traceTiny("mkProc", "writeback","W");

   548      

   549 

   550     // get what to do off the writeback queue

   551      wbQ.deq();

   552      case (wbQ.first()) matches

   553 	tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);

   554 	tagged WB_Load .regWr : 

   555 	   begin

   556 	      dataRespQ.deq();

   557 	      if (dataRespQ.first() matches tagged LoadResp .ld)

   558 		rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue?  Duplicate?

   559 	   end

   560 	tagged WB_Store : dataRespQ.deq();

   561 	tagged WB_Host .dat : noAction;

   562      endcase

   563            

   564   endrule

   565 

   566 //rlm remove

   567  // rule inc_num_cycles;

   568  //   if ( cp0_statsEn )

   569  //     num_cycles.incr();

   570  // endrule

   571 

   572 /*

   573  // for now, we don't do anything.

   574   rule connectAudioReqResp;

   575     $display("rlm: PROCESSOR copies a datum\n");

   576     outAudioFifo.enq(inAudioFifo.first());

   577     inAudioFifo.deq;

   578   endrule

   579 */

   580 

   581   rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile);

   582      $display (" PROCESSOR End Audio Flag Set ");

   583      cp0_audioEOF <= True;

   584      inAudioFifo.deq;

   585   endrule

   586 

   587   rule sendAudioEnd (cp0_progComp);

   588      $display (" PROCESSOR Says Program Complete ");

   589      outAudioFifo.enq(tagged EndOfFile);

   590      cp0_progComp <= False;  //only send one.  And functions to reset

   591   endrule

   592 

   593    

   594   //-----------------------------------------------------------

   595   // Methods

   596 

   597   interface Client imem_client;

   598     interface Get request  = fifoToGet(instReqQ);

   599     interface Put response = fifoToPut(instRespQ);

   600   endinterface

   601 

   602   interface Client dmem_client;

   603     interface Get request  = fifoToGet(dataReqQ);

   604     interface Put response = fifoToPut(dataRespQ);

   605   endinterface

   606 

   607   interface Get statsEn_get = toGet(asReg(cp0_statsEn));

   608 

   609   /*

   610   interface CPUToHost tohost;

   611     method Bit#(32) cpuToHost(int req);

   612       return (case (req)

   613        0: cp0_tohost;

   614        1: pc;

   615        2: zeroExtend(pack(stage));

   616       endcase);

   617     endmethod

   618   endinterface

   619   */

   620    

   621   interface Get sampleOutput = fifoToGet(outAudioFifo);

   622   interface Put sampleInput = fifoToPut(inAudioFifo);

   623 

   624 endmodule

   625
author	rlm
date	Wed, 05 May 2010 14:40:48 -0400
parents	4d87fa55a776
children	2b18894f75e2