view core/sim/bdir_dut/Bridge.bi @ 58:52f9a257c2ba pygar svn.59

[svn r59] LUTRAMing
author punk
date Mon, 10 May 2010 13:47:12 -0400
parents 91a1f76ddd62
children
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1 signature Bridge where {
2 import ¶Assert®¶;
4 import ¶ConfigReg®¶;
6 import ¶Counter®¶;
8 import ¶DReg®¶;
10 import ¶EdgeDetect®¶;
12 import ¶FIFOF_®¶;
14 import ¶FIFOF®¶;
16 import ¶FIFO®¶;
18 import ¶HList®¶;
20 import ¶Inout®¶;
22 import ¶List®¶;
24 import BFIFO;
26 import ¶Clocks®¶;
28 import ¶DiniPCIE®¶;
30 import ¶ListN®¶;
32 import ¶ModuleContextCore®¶;
34 import ¶ModuleContext®¶;
36 import ¶Monad®¶;
38 import ¶PrimArray®¶;
40 import ¶RWire®¶;
42 import ¶RegFile®¶;
44 import ¶Real®¶;
46 import ¶RevertingVirtualReg®¶;
48 import ¶Reserved®¶;
50 import SFIFO;
52 import ¶Vector®¶;
54 import ¶BRAMCore®¶;
56 import ¶BUtils®¶;
58 import ¶Connectable®¶;
60 import ¶DefaultValue®¶;
62 import ¶Gearbox®¶;
64 import ¶GetPut®¶;
66 import ¶AlignedFIFOs®¶;
68 import ¶ClientServer®¶;
70 import ¶FIFOLevel®¶;
72 import ¶SceMiDefines®¶;
74 import ¶SceMiProxies®¶;
76 import ¶SpecialFIFOs®¶;
78 import ¶SceMiInternals®¶;
80 import ¶SceMiAldecMacros®¶;
82 import ¶SceMiEveMacros®¶;
84 import ¶SceMiMacros®¶;
86 import ¶TieOff®¶;
88 import Trace;
90 import MemTypes;
92 import MemArb;
94 import ProcTypes;
96 import BRegFile;
98 import BranchPred;
100 import DataCacheBlocking;
102 import InstCacheBlocking;
104 import Processor;
106 import Core;
108 import ¶UnitAppendList®¶;
110 import ¶XilinxCells®¶;
112 import ¶SceMiClocks®¶;
114 import ¶SceMiDiniPCIE®¶;
116 import ¶SceMiTCP®¶;
118 import ¶XilinxPCIE®¶;
120 import ¶SceMiVirtex5PCIE®¶;
122 import ¶SceMiPCIE®¶;
124 import ¶SceMiCore®¶;
126 import ¶SceMiXactors®¶;
128 import ¶SceMiSerialProbe®¶;
130 import ¶SceMi®¶;
132 import SceMiLayer;
134 Bridge.lt :: ¶SceMiDefines®¶.¶SceMiLinkType®¶;
136 Bridge.mkBridge :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ ¶Prelude®¶.¶Empty®¶
137 }