view core/sim/bdir_dut/MemArb.bi @ 52:49049f97312c pygar svn.53

[svn r53] sends to two cores (but has issues)
author punk
date Thu, 06 May 2010 08:57:53 -0400
parents 91a1f76ddd62
children
line wrap: on
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1 signature MemArb where {
2 import ¶Assert®¶;
4 import ¶Counter®¶;
6 import ¶FIFOF_®¶;
8 import ¶FIFOF®¶;
10 import ¶FIFO®¶;
12 import ¶Inout®¶;
14 import ¶List®¶;
16 import BFIFO;
18 import ¶Clocks®¶;
20 import ¶ListN®¶;
22 import ¶PrimArray®¶;
24 import ¶Vector®¶;
26 import ¶Connectable®¶;
28 import ¶GetPut®¶;
30 import ¶ClientServer®¶;
32 import Trace;
34 import MemTypes;
36 interface (MemArb.MemArb :: *) = {
37 MemArb.cache0_server :: ¶ClientServer®¶.¶Server®¶ MemTypes.MainMemReq MemTypes.MainMemResp;
38 MemArb.cache1_server :: ¶ClientServer®¶.¶Server®¶ MemTypes.MainMemReq MemTypes.MainMemResp;
39 MemArb.mmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.MainMemReq MemTypes.MainMemResp
40 };
42 instance MemArb ¶Prelude®¶.¶PrimMakeUndefined®¶ MemArb.MemArb;
44 instance MemArb ¶Prelude®¶.¶PrimDeepSeqCond®¶ MemArb.MemArb;
46 instance MemArb ¶Prelude®¶.¶PrimMakeUninitialized®¶ MemArb.MemArb;
48 data (MemArb.ReqPtr :: *) = MemArb.REQ0 () | MemArb.REQ1 ();
50 instance MemArb ¶Prelude®¶.¶PrimMakeUndefined®¶ MemArb.ReqPtr;
52 instance MemArb ¶Prelude®¶.¶PrimDeepSeqCond®¶ MemArb.ReqPtr;
54 instance MemArb ¶Prelude®¶.¶PrimMakeUninitialized®¶ MemArb.ReqPtr;
56 instance MemArb ¶Prelude®¶.¶Eq®¶ MemArb.ReqPtr;
58 instance MemArb ¶Prelude®¶.¶Bits®¶ MemArb.ReqPtr 1;
60 MemArb.mkMemArb :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ MemArb.MemArb
61 }