Mercurial > pygar
view modules/bluespec/Pygar/lab4/BRegFile.bsv @ 68:44cc00df1168 pygar svn.69
[svn r69] runs separate eofs (I think)
author | punk |
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date | Wed, 12 May 2010 00:06:05 -0400 |
parents | 1d5cbb5343d2 |
children |
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1 import RegFile::*;2 import RWire::*;3 import ProcTypes::*;5 `include "asim/provides/low_level_platform_interface.bsh"6 `include "asim/provides/soft_connections.bsh"7 `include "asim/provides/fpga_components.bsh"8 `include "asim/provides/common_services.bsh"10 //-----------------------------------------------------------11 // Register file module12 //-----------------------------------------------------------14 interface BRegFile;15 method Action wr( Rindx rindx, Bit#(32) data );16 method ActionValue#( Bit#(32)) rd1( Rindx rindx );17 method ActionValue#( Bit#(32)) rd2( Rindx rindx );18 endinterface20 (* doc = "synthesis attribute ram_style mkBRegFile distributed;" *)21 (* synthesize *)22 module mkBRegFile(BRegFile);24 LUTRAM#(Rindx, Bit#(32)) rf <- mkLUTRAMU_RegFile();25 RWire#(Tuple2#(Rindx, Bit#(32))) rw <-mkRWire();27 method Action wr( Rindx rindx, Bit#(32) data );28 rf.upd( rindx, data );29 rw.wset(tuple2(rindx,data));30 endmethod32 method ActionValue#(Bit#(32)) rd1 (Rindx r);33 if (r == 0) return 0;34 else begin35 case (rw.wget()) matches36 tagged Valid {.wr, .d} :37 return (wr == r) ? d : rf.sub(r);38 tagged Invalid : return rf.sub(r);39 endcase40 end41 endmethod43 method ActionValue#(Bit#(32)) rd2 (Rindx r);44 if (r == 0) return 0;45 else begin46 case (rw.wget()) matches47 tagged Valid {.wr, .d} :48 return (wr == r) ? d : rf.sub(r);49 tagged Invalid : return rf.sub(r);50 endcase51 end52 endmethod54 endmodule