signature SceMiLayer where {

 import ¶Assert®¶;

 		

 import ¶ConfigReg®¶;

 		   

 import ¶Counter®¶;

 		 

 import ¶DReg®¶;

 	      

 import ¶EdgeDetect®¶;

 		    

 import ¶FIFOF_®¶;

 		

 import ¶FIFOF®¶;

 	       

 import ¶FIFO®¶;

 	      

 import ¶HList®¶;

 	       

 import ¶Inout®¶;

 	       

 import ¶List®¶;

 	      

 import BFIFO;

 	    

 import ¶Clocks®¶;

 		

 import ¶DiniPCIE®¶;

 		  

 import ¶ListN®¶;

 	       

 import ¶ModuleContextCore®¶;

 			   

 import ¶ModuleContext®¶;

 		       

 import ¶Monad®¶;

 	       

 import ¶PrimArray®¶;

 		   

 import ¶RWire®¶;

 	       

 import ¶RegFile®¶;

 		 

 import ¶Real®¶;

 	      

 import ¶RevertingVirtualReg®¶;

 			     

 import ¶Reserved®¶;

 		  

 import SFIFO;

 	    

 import ¶Vector®¶;

 		

 import ¶BRAMCore®¶;

 		  

 import ¶BUtils®¶;

 		

 import ¶Connectable®¶;

 		     

 import ¶DefaultValue®¶;

 		      

 import ¶Gearbox®¶;

 		 

 import ¶GetPut®¶;

 		

 import ¶AlignedFIFOs®¶;

 		      

 import ¶ClientServer®¶;

 		      

 import ¶FIFOLevel®¶;

 		   

 import ¶SceMiDefines®¶;

 		      

 import ¶SceMiProxies®¶;

 		      

 import ¶SpecialFIFOs®¶;

 		      

 import ¶SceMiInternals®¶;

 			

 import ¶SceMiAldecMacros®¶;

 			  

 import ¶SceMiEveMacros®¶;

 			

 import ¶SceMiMacros®¶;

 		     

 import ¶TieOff®¶;

 		

 import Trace;

 	    

 import MemTypes;

 	       

 import MemArb;

 	     

 import ProcTypes;

 		

 import BRegFile;

 	       

 import BranchPred;

 		 

 import DataCacheBlocking;

 			

 import InstCacheBlocking;

 			

 import Processor;

 		

 import Core;

 	   

 import ¶UnitAppendList®¶;

 			

 import ¶XilinxCells®¶;

 		     

 import ¶SceMiClocks®¶;

 		     

 import ¶SceMiDiniPCIE®¶;

 		       

 import ¶SceMiTCP®¶;

 		  

 import ¶XilinxPCIE®¶;

 		    

 import ¶SceMiVirtex5PCIE®¶;

 			  

 import ¶SceMiPCIE®¶;

 		   

 import ¶SceMiCore®¶;

 		   

 import ¶SceMiXactors®¶;

 		      

 import ¶SceMiSerialProbe®¶;

 			  

 import ¶SceMi®¶;

 	       

 interface (SceMiLayer.DutWrapper :: *) = {

     SceMiLayer.core :: Core.Core;

     SceMiLayer.doreset :: ¶GetPut®¶.¶Put®¶ (¶Prelude®¶.¶Bit®¶ 1)

 };

  

 instance SceMiLayer ¶Prelude®¶.¶PrimMakeUndefined®¶ SceMiLayer.DutWrapper;

 									 

 instance SceMiLayer ¶Prelude®¶.¶PrimDeepSeqCond®¶ SceMiLayer.DutWrapper;

 								       

 instance SceMiLayer ¶Prelude®¶.¶PrimMakeUninitialized®¶ SceMiLayer.DutWrapper;

 									     

 SceMiLayer.mkDutWrapper :: ¶Prelude®¶.¶Module®¶ SceMiLayer.DutWrapper;

 								     

 SceMiLayer.mkSceMiLayer :: ¶SceMiInternals®¶.¶SceMiModule®¶ ¶Prelude®¶.¶Empty®¶;

 									       

 SceMiLayer.mkCPUToHostXactor :: Processor.CPUToHost ->

 				¶SceMiDefines®¶.¶SceMiClockPortIfc®¶ ->

 				¶SceMiInternals®¶.¶SceMiModule®¶ ¶Prelude®¶.¶Empty®¶;

 										    

 data (SceMiLayer.StatID :: *) =

     SceMiLayer.DCACHE_ACCESSES () |

     SceMiLayer.DCACHE_MISSES () |

     SceMiLayer.DCACHE_WRITEBACKS () |

     SceMiLayer.ICACHE_ACCESSES () |

     SceMiLayer.ICACHE_MISSES () |

     SceMiLayer.ICACHE_EVICTIONS () |

     SceMiLayer.PROC_INST () |

     SceMiLayer.PROC_CYCLES ();

 			     

 instance SceMiLayer ¶Prelude®¶.¶PrimMakeUndefined®¶ SceMiLayer.StatID;

 								     

 instance SceMiLayer ¶Prelude®¶.¶PrimDeepSeqCond®¶ SceMiLayer.StatID;

 								   

 instance SceMiLayer ¶Prelude®¶.¶PrimMakeUninitialized®¶ SceMiLayer.StatID;

 									 

 instance SceMiLayer ¶Prelude®¶.¶Bits®¶ SceMiLayer.StatID 3;

 							  

 instance SceMiLayer ¶Prelude®¶.¶Eq®¶ SceMiLayer.StatID;

 						      

 SceMiLayer.mkCoreStatsXactor :: Core.CoreStats ->

 				¶SceMiDefines®¶.¶SceMiClockPortIfc®¶ ->

 				¶SceMiInternals®¶.¶SceMiModule®¶ ¶Prelude®¶.¶Empty®¶

 }