view modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv @ 50:2b18894f75e2 pygar svn.51

[svn r51] fixed processor- it works
author punk
date Wed, 05 May 2010 15:19:32 -0400
parents 61f6267cb3db
children 9fe5ed4af92d
line wrap: on
line source
1 // The MIT License
3 // Copyright (c) 2009 Massachusetts Institute of Technology
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
23 // Local includes
24 `include "asim/provides/low_level_platform_interface.bsh"
25 `include "asim/provides/soft_connections.bsh"
26 `include "asim/provides/processor_library.bsh"
27 `include "asim/provides/fpga_components.bsh"
28 `include "asim/provides/common_services.bsh"
29 `include "asim/dict/STATS_DATA_CACHE.bsh"
31 import Connectable::*;
32 import GetPut::*;
33 import ClientServer::*;
34 import RegFile::*;
35 import FIFO::*;
36 import FIFOF::*;
37 import Trace::*;
39 interface DCache#( type req_t, type resp_t );
41 // Interface from processor to cache
42 interface Server#(req_t,resp_t) proc_server;
44 // Interface from cache to main memory
45 interface Client#(MainMemReq,MainMemResp) mmem_client;
47 // Interface for enabling/disabling statistics
48 interface Put#(Bool) statsEn_put;
50 endinterface
53 //----------------------------------------------------------------------
54 // Cache Types
55 //----------------------------------------------------------------------
57 typedef 10 CacheLineIndexSz;
58 typedef 20 CacheLineTagSz;
59 typedef 32 CacheLineSz;
61 typedef Bit#(CacheLineIndexSz) CacheLineIndex;
62 typedef Bit#(CacheLineTagSz) CacheLineTag;
63 typedef Bit#(CacheLineSz) CacheLine;
65 typedef enum
66 {
67 Init,
68 Access,
69 RefillReq,
70 RefillResp
71 }
72 CacheStage
73 deriving (Eq,Bits);
75 //----------------------------------------------------------------------
76 // Helper functions
77 //----------------------------------------------------------------------
79 function Bit#(AddrSz) getAddr( DataReq req );
81 Bit#(AddrSz) addr = ?;
82 case ( req ) matches
83 tagged LoadReq .ld : addr = ld.addr;
84 tagged StoreReq .st : addr = st.addr;
85 endcase
87 return addr;
89 endfunction
91 function CacheLineIndex getCacheLineIndex( DataReq req );
92 Bit#(AddrSz) addr = getAddr(req);
93 Bit#(CacheLineIndexSz) index = truncate( addr >> 2 );
94 return index;
95 endfunction
97 function CacheLineTag getCacheLineTag( DataReq req );
98 Bit#(AddrSz) addr = getAddr(req);
99 Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 );
100 return tag;
101 endfunction
103 function Bit#(AddrSz) getCacheLineAddr( DataReq req );
104 Bit#(AddrSz) addr = getAddr(req);
105 return ((addr >> 2) << 2);
106 endfunction
108 //----------------------------------------------------------------------
109 // Main module
110 //----------------------------------------------------------------------
112 module [CONNECTED_MODULE] mkDataCache( DCache#(DataReq,DataResp) );
114 //-----------------------------------------------------------
115 // State
117 Reg#(CacheStage) stage <- mkReg(Init);
119 LUTRAM#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkLUTRAMU_RegFile();
120 LUTRAM#(CacheLineIndex,CacheLine) cacheDataRam <- mkLUTRAMU_RegFile();
122 FIFO#(DataReq) reqQ <- mkFIFO();
123 FIFOF#(DataResp) respQ <- mkBFIFOF1();
125 FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1();
126 FIFO#(MainMemResp) mainMemRespQ <- mkFIFO();
128 Reg#(CacheLineIndex) initCounter <- mkReg(1);
130 // Statistics state
132 Reg#(Bool) statsEn <- mkReg(False);
133 //rlm:
134 //STAT num_accesses <- mkStatCounter(`STATS_DATA_CACHE_NUM_ACCESSES);
135 //STAT num_misses <- mkStatCounter(`STATS_DATA_CACHE_NUM_MISSES);
136 //STAT num_writebacks <- mkStatCounter(`STATS_DATA_CACHE_NUM_WRITEBACKS);
138 //-----------------------------------------------------------
139 // Name some wires
141 let req = reqQ.first();
142 let reqIndex = getCacheLineIndex(req);
143 let reqTag = getCacheLineTag(req);
144 let reqCacheLineAddr = getCacheLineAddr(req);
146 //-----------------------------------------------------------
147 // Initialize
149 rule init ( stage == Init );
150 traceTiny("mkDataCacheBlocking", "stage","i");
151 initCounter <= initCounter + 1;
152 cacheTagRam.upd(initCounter,Invalid);
153 if ( initCounter == 0 )
154 stage <= Access;
155 endrule
157 //-----------------------------------------------------------
158 // Access cache rule
160 rule access ( (stage == Access) && respQ.notFull() );
162 // Statistics
163 //rlm:
164 //if ( statsEn )
165 // num_accesses.incr();
168 // Get the corresponding tag from the rams
170 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);
172 // Handle cache hits ...
174 if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) )
175 begin
176 traceTiny("mkDataCacheBlocking", "hitMiss","h");
177 reqQ.deq();
179 case ( req ) matches
181 tagged LoadReq .ld :
182 respQ.enq( LoadResp { tag: ld.tag, data: cacheDataRam.sub(reqIndex) } );
184 tagged StoreReq .st :
185 begin
186 respQ.enq( StoreResp { tag : st.tag } );
187 cacheDataRam.upd(reqIndex,st.data);
188 end
190 endcase
192 end
194 // Handle cache misses ...
196 else
197 begin
198 traceTiny("mkDataCacheBlocking", "hitMiss","m");
199 //rlm:
200 //if ( statsEn )
201 // num_misses.incr();
203 // Currently we don't use dirty bits so we always writeback the data if it is valid
205 if ( isValid(cacheLineTag) )
206 begin
207 //rlm:
208 // if ( statsEn )
209 // num_writebacks.incr();
211 MainMemReq wbReq
212 = StoreReq { tag : 0,
213 addr : { unJust(cacheLineTag), reqIndex, 2'b0 },
214 data : cacheDataRam.sub(reqIndex) };
216 mainMemReqQ.enq(wbReq);
217 stage <= RefillReq;
218 end
220 // Otherwise we can issue the refill request now
222 else
223 begin
224 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } );
225 stage <= RefillResp;
226 end
228 end
230 endrule
232 //-----------------------------------------------------------
233 // Refill request rule
235 rule refillReq ( stage == RefillReq );
236 traceTiny("mkDataCacheBlocking", "stage","r");
237 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } );
238 stage <= RefillResp;
239 endrule
241 //-----------------------------------------------------------
242 // Refill response rule
244 rule refillResp ( stage == RefillResp );
245 traceTiny("mkDataCacheBlocking", "stage","R");
246 traceTiny("mkDataCacheBlocking", "refill",mainMemRespQ.first());
248 // Write the new data into the cache and update the tag
250 mainMemRespQ.deq();
251 case ( mainMemRespQ.first() ) matches
253 tagged LoadResp .ld :
254 begin
255 cacheTagRam.upd(reqIndex,Valid(reqTag));
256 cacheDataRam.upd(reqIndex,ld.data);
257 end
259 tagged StoreResp .st :
260 noAction;
262 endcase
264 stage <= Access;
265 endrule
267 //-----------------------------------------------------------
268 // Methods
270 interface Client mmem_client;
271 interface Get request = fifoToGet(mainMemReqQ);
272 interface Put response = fifoToPut(mainMemRespQ);
273 endinterface
275 interface Server proc_server;
276 interface Put request = tracePut("mkDataCacheBlocking", "reqTiny",fifoToPut(reqQ));
277 interface Get response = traceGet("mkDataCacheBlocking", "respTiny",fifofToGet(respQ));
278 endinterface
280 interface Put statsEn_put = regToPut(statsEn);
282 endmodule