Mercurial > pygar
view core/src/InstCacheBlocking.bsv @ 53:2991344775f8 pygar svn.54
[svn r54] mixer integrated
author | punk |
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date | Sun, 09 May 2010 10:58:40 -0400 |
parents | 91a1f76ddd62 |
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1 // The MIT License3 // Copyright (c) 2009 Massachusetts Institute of Technology5 // Permission is hereby granted, free of charge, to any person obtaining a copy6 // of this software and associated documentation files (the "Software"), to deal7 // in the Software without restriction, including without limitation the rights8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell9 // copies of the Software, and to permit persons to whom the Software is10 // furnished to do so, subject to the following conditions:12 // The above copyright notice and this permission notice shall be included in13 // all copies or substantial portions of the Software.15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN21 // THE SOFTWARE.23 import Connectable::*;24 import GetPut::*;25 import ClientServer::*;26 import RegFile::*;27 import FIFO::*;28 import FIFOF::*;29 import RWire::*;31 import BFIFO::*;32 import MemTypes::*;33 import ProcTypes::*;34 import Trace::*;36 interface ICacheStats;37 interface Get#(Stat) num_accesses;38 interface Get#(Stat) num_misses;39 interface Get#(Stat) num_evictions;40 endinterface42 interface ICache#( type req_t, type resp_t );44 // Interface from processor to cache45 interface Server#(req_t,resp_t) proc_server;47 // Interface from cache to main memory48 interface Client#(MainMemReq,MainMemResp) mmem_client;50 // Interface for enabling/disabling statistics51 interface Put#(Bool) statsEn_put;53 // Interface for collecting statistics54 interface ICacheStats stats;56 endinterface58 //----------------------------------------------------------------------59 // Cache Types60 //----------------------------------------------------------------------62 typedef 10 CacheLineIndexSz;63 typedef 20 CacheLineTagSz;64 typedef 32 CacheLineSz;66 typedef Bit#(CacheLineIndexSz) CacheLineIndex;67 typedef Bit#(CacheLineTagSz) CacheLineTag;68 typedef Bit#(CacheLineSz) CacheLine;70 typedef enum71 {72 Init,73 Access,74 Evict,75 RefillReq,76 RefillResp77 }78 CacheStage79 deriving (Eq,Bits);81 //----------------------------------------------------------------------82 // Helper functions83 //----------------------------------------------------------------------85 function Bit#(AddrSz) getAddr( InstReq req );87 Bit#(AddrSz) addr = ?;88 case ( req ) matches89 tagged LoadReq .ld : addr = ld.addr;90 tagged StoreReq .st : addr = st.addr;91 endcase93 return addr;95 endfunction97 function CacheLineIndex getCacheLineIndex( InstReq req );98 Bit#(AddrSz) addr = getAddr(req);99 Bit#(CacheLineIndexSz) index = truncate( addr >> 2 );100 return index;101 endfunction103 function CacheLineTag getCacheLineTag( InstReq req );104 Bit#(AddrSz) addr = getAddr(req);105 Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 );106 return tag;107 endfunction109 function Bit#(AddrSz) getCacheLineAddr( InstReq req );110 Bit#(AddrSz) addr = getAddr(req);111 return ((addr >> 2) << 2);112 endfunction114 //----------------------------------------------------------------------115 // Main module116 //----------------------------------------------------------------------118 (* doc = "synthesis attribute ram_style mkInstCache distributed;" *)119 (* synthesize *)120 module mkInstCache( ICache#(InstReq,InstResp) );122 //-----------------------------------------------------------123 // State125 Reg#(CacheStage) stage <- mkReg(Init);127 RegFile#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkRegFileFull();128 RegFile#(CacheLineIndex,CacheLine) cacheDataRam <- mkRegFileFull();130 FIFO#(InstReq) reqQ <- mkFIFO();131 FIFOF#(InstResp) respQ <- mkBFIFOF1();133 FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1();134 FIFO#(MainMemResp) mainMemRespQ <- mkFIFO();136 Reg#(CacheLineIndex) initCounter <- mkReg(1);138 // Statistics state140 Reg#(Bool) statsEn <- mkReg(False);142 Reg#(Stat) numAccesses <- mkReg(0);143 Reg#(Stat) numMisses <- mkReg(0);144 Reg#(Stat) numEvictions <- mkReg(0);146 //-----------------------------------------------------------147 // Name some wires149 let req = reqQ.first();150 let reqIndex = getCacheLineIndex(req);151 let reqTag = getCacheLineTag(req);152 let reqCacheLineAddr = getCacheLineAddr(req);153 let refill = mainMemRespQ.first();155 //-----------------------------------------------------------156 // Initialize158 rule init ( stage == Init );159 traceTiny("mkInstCacheBlocking", "stage","i");160 initCounter <= initCounter + 1;161 cacheTagRam.upd(initCounter,Invalid);162 if ( initCounter == 0 )163 stage <= Access;164 endrule166 //-----------------------------------------------------------167 // Cache access rule169 rule access ( (stage == Access) && respQ.notFull() );171 // Statistics173 if ( statsEn )174 numAccesses <= numAccesses + 1;176 // Check tag and valid bit to see if this is a hit or a miss178 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);180 // Handle cache hits ...182 if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) )183 begin184 traceTiny("mkInstCacheBlocking", "hitMiss","h");185 reqQ.deq();187 case ( req ) matches189 tagged LoadReq .ld :190 respQ.enq( LoadResp { tag : ld.tag, data : cacheDataRam.sub(reqIndex) } );192 tagged StoreReq .st :193 $display( " RTL-ERROR : %m : Stores are not allowed on the inst port!" );195 endcase197 end199 // Handle cache misses - since lines in instruction cache are200 // never dirty we can always immediately issue a refill request202 else203 begin204 traceTiny("mkInstCacheBlocking", "hitMiss","m");205 if ( statsEn )206 numMisses <= numMisses + 1;207 if ( statsEn )208 if ( isJust(cacheLineTag) )209 numEvictions <= numEvictions + 1;211 MainMemReq rfReq212 = LoadReq { tag : 0,213 addr : reqCacheLineAddr };215 mainMemReqQ.enq(rfReq);216 stage <= RefillResp;217 end219 endrule221 //-----------------------------------------------------------222 // Refill response rule224 rule refillResp ( stage == RefillResp );225 traceTiny("mkInstCacheBlocking", "stage","R");226 traceTiny("mkInstCacheBlocking", "refill",refill);228 // Write the new data into the cache and update the tag230 mainMemRespQ.deq();231 case ( mainMemRespQ.first() ) matches233 tagged LoadResp .ld :234 begin235 cacheTagRam.upd(reqIndex,Valid(reqTag));236 cacheDataRam.upd(reqIndex,ld.data);237 end239 tagged StoreResp .st :240 noAction;242 endcase244 stage <= Access;245 endrule247 //-----------------------------------------------------------248 // Methods250 interface Client mmem_client;251 interface Get request = fifoToGet(mainMemReqQ);252 interface Put response = fifoToPut(mainMemRespQ);253 endinterface255 interface Server proc_server;256 interface Put request = tracePut("mkInstCacheBlocking", "reqTiny",toPut(reqQ));257 interface Get response = traceGet("mkInstCacheBlocking", "respTiny",toGet(respQ));258 endinterface260 interface Put statsEn_put = toPut(asReg(statsEn));262 interface ICacheStats stats;263 interface Get num_accesses = toGet(asReg(numAccesses));264 interface Get num_misses = toGet(asReg(numMisses));265 interface Get num_evictions = toGet(asReg(numEvictions));266 endinterface268 endmodule