Mercurial > pygar
view core/sim/bdir_dut/Processor.bi @ 25:220c14f5963c pygar svn.26
[svn r26] Not fully connected but passes audio successfully
author | punk |
---|---|
date | Wed, 28 Apr 2010 12:01:37 -0400 |
parents | 91a1f76ddd62 |
children |
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1 signature Processor where {2 import ¶Assert®¶;4 import ¶ConfigReg®¶;6 import ¶Counter®¶;8 import ¶FIFOF_®¶;10 import ¶FIFOF®¶;12 import ¶FIFO®¶;14 import ¶Inout®¶;16 import ¶List®¶;18 import BFIFO;20 import ¶Clocks®¶;22 import ¶ListN®¶;24 import ¶Monad®¶;26 import ¶PrimArray®¶;28 import ¶RWire®¶;30 import ¶RegFile®¶;32 import SFIFO;34 import ¶Vector®¶;36 import ¶Connectable®¶;38 import ¶GetPut®¶;40 import ¶ClientServer®¶;42 import Trace;44 import MemTypes;46 import ProcTypes;48 import BRegFile;50 import BranchPred;52 interface (Processor.ProcStats :: *) = {53 Processor.num_cycles :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat;54 Processor.num_inst :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat55 };57 instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.ProcStats;59 instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.ProcStats;61 instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.ProcStats;63 interface (Processor.CPUToHost :: *) = {64 Processor.cpuToHost :: ¶Prelude®¶.¶Int®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32 {-# arg_names = [req] #-}65 };67 instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.CPUToHost;69 instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.CPUToHost;71 instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.CPUToHost;73 interface (Processor.Proc :: *) = {74 Processor.dmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.DataReq MemTypes.DataResp;75 Processor.imem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.InstReq MemTypes.InstResp;76 Processor.statsEn_get :: ¶GetPut®¶.¶Get®¶ ¶Prelude®¶.¶Bool®¶;77 Processor.stats :: Processor.ProcStats;78 Processor.tohost :: Processor.CPUToHost79 };81 instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.Proc;83 instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.Proc;85 instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.Proc;87 data (Processor.Stage :: *) = Processor.PCgen () | Processor.Exec () | Processor.Writeback ();89 instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.Stage;91 instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.Stage;93 instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.Stage;95 instance Processor ¶Prelude®¶.¶Eq®¶ Processor.Stage;97 instance Processor ¶Prelude®¶.¶Bits®¶ Processor.Stage 2;99 interface (Processor.BRFile :: *) = {100 Processor.wr :: ProcTypes.Rindx ->101 ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Action®¶ {-# arg_names = [rindx, ¡data¡] #-};102 Processor.rd1 :: ProcTypes.Rindx -> ¶Prelude®¶.¶Bit®¶ 32 {-# arg_names = [rindx] #-};103 Processor.rd2 :: ProcTypes.Rindx -> ¶Prelude®¶.¶Bit®¶ 32 {-# arg_names = [rindx] #-}104 };106 instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.BRFile;108 instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.BRFile;110 instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.BRFile;112 Processor.mkBRFile :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ Processor.BRFile;114 Processor.slt :: ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32;116 Processor.sltu :: ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32;118 Processor.rshft :: ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32;120 Processor.findwbf :: ProcTypes.Rindx -> ProcTypes.WBResult -> ¶Prelude®¶.¶Bool®¶;122 Processor.stall :: ProcTypes.Instr ->123 SFIFO.SFIFO ProcTypes.WBResult ProcTypes.Rindx -> ¶Prelude®¶.¶Bool®¶;125 Processor.mkProc :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ Processor.Proc126 }