Mercurial > pygar

     1 // The MIT License

     2 

     3 // Copyright (c) 2009 Massachusetts Institute of Technology

     4 

     5 // Permission is hereby granted, free of charge, to any person obtaining a copy

     6 // of this software and associated documentation files (the "Software"), to deal

     7 // in the Software without restriction, including without limitation the rights

     8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

     9 // copies of the Software, and to permit persons to whom the Software is

    10 // furnished to do so, subject to the following conditions:

    11 

    12 // The above copyright notice and this permission notice shall be included in

    13 // all copies or substantial portions of the Software.

    14 

    15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

    16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

    17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

    18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

    19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

    20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

    21 // THE SOFTWARE.

    22 

    23 import Connectable::*;

    24 import GetPut::*;

    25 import ClientServer::*;

    26 import Processor::*;

    27 import MemArb::*;

    28 import MemTypes::*;

    29 import FIFO::*;

    30 

    31 //AWB includes

    32 `include "asim/provides/low_level_platform_interface.bsh"

    33 `include "asim/provides/soft_connections.bsh"

    34 `include "asim/provides/common_services.bsh"

    35 

    36 // Local includes

    37 `include "asim/provides/processor_library.bsh"

    38 `include "asim/provides/mem_arb.bsh"

    39 `include "asim/provides/instruction_cache.bsh"

    40 `include "asim/provides/data_cache.bsh"

    41 `include "asim/provides/processor.bsh"

    42 `include "asim/provides/audio_pipe_types.bsh"

    43 

    44 // Scratchpad includes

    45 `include "asim/provides/scratchpad_memory.bsh"

    46 `include "asim/provides/mem_services.bsh"

    47 `include "asim/dict/VDEV_SCRATCH.bsh"

    48 

    49 interface Core;

    50 

    51    interface Get#(AudioProcessorUnit) sampleOutput;

    52    interface Put#(AudioProcessorUnit) sampleInput;

    53 	 

    54 //   interface CPUToHost tohost;

    55    

    56 endinterface

    57 

    58 module   [CONNECTED_MODULE]  mkCore#(Integer prog) ( Core );

    59    

    60 

    61   // Instantiate the modules

    62 

    63   Proc proc <- mkProc();

    64   ICache#(InstReq,InstResp) icache <- mkInstCache();

    65   DCache#(DataReq,DataResp) dcache <- mkDataCache();

    66   MemArb marb <- mkMemArb();

    67   MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(prog, SCRATCHPAD_CACHED);   //Services Memory items

    68 

    69   // Make this big enough so that several outstanding requests may be supported

    70   FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);

    71    

    72   // Internal connections

    73 

    74   mkConnection( proc.statsEn_get,   icache.statsEn_put );

    75   mkConnection( proc.statsEn_get,   dcache.statsEn_put );

    76   mkConnection( proc.imem_client,   icache.proc_server );

    77   mkConnection( proc.dmem_client,   dcache.proc_server );

    78   mkConnection( icache.mmem_client, marb.cache0_server );

    79   mkConnection( dcache.mmem_client, marb.cache1_server );

    80 

    81   // Memory Access

    82   rule sendMemReq;

    83     let coreReq <- marb.mmem_client.request.get;

    84     case (coreReq) matches 

    85       tagged LoadReq .load: begin

    86 	                      $display("CORE: Load Addr Req %h", load.addr); 

    87                               //Allocate ROB space

    88                               memory.readReq(truncate(load.addr>>2));

    89                               tags.enq(load.tag);

    90                             end

    91       tagged StoreReq .store: begin

    92 	  	              $display("CORE: Write Addr Req %h", store.addr); 

    93 	                      memory.write(truncate(store.addr>>2),store.data);

    94                               end

    95     endcase

    96   endrule

    97   

    98   rule receiveMemResp;

    99     let memResp <- memory.readRsp();

   100     tags.deq;

   101     marb.mmem_client.response.put(tagged LoadResp {data:memResp,

   102                                                    tag: tags.first});

   103    	                $display("CORE: Receive MemReq %x", memResp); 

   104   endrule

   105 

   106   // Methods

   107      

   108    interface sampleOutput = proc.sampleOutput;

   109    interface sampleInput = proc.sampleInput;

   110 

   111 //   interface CPUToHost tohost = proc.tohost;

   112 

   113 endmodule
author	rlm
date	Tue, 11 May 2010 23:23:21 -0400
parents	cf8bb3038cbd
children	44cc00df1168