view modules/bluespec/Pygar/core/audioCorePipeline.bsv @ 22:0cfbb1e2de22 pygar svn.23

[svn r23] whoohoo! it Compiles (note with commented out stuff)
author punk
date Wed, 28 Apr 2010 00:40:15 -0400
parents a1833d9f6e3d
children 220c14f5963c
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1 // The MIT License
3 // Copyright (c) 2009 Massachusetts Institute of Technology
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
23 // Author: Kermin Fleming kfleming@mit.edu
25 import Connectable::*;
26 import GetPut::*;
27 import ClientServer::*;
28 import FIFO::*;
29 import SpecialFIFOs::*;
31 //AWB includes
32 `include "asim/provides/low_level_platform_interface.bsh"
33 `include "asim/provides/soft_connections.bsh"
34 `include "asim/provides/common_services.bsh"
36 //Local includes
37 `include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface
38 `include "asim/provides/core.bsh"
39 `include "asim/provides/processor_library.bsh"
40 `include "asim/provides/fpga_components.bsh"
41 `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"
42 //`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
44 module [CONNECTED_MODULE] mkConnectedApplication ();
45 Core core <- mkCore;
46 Reg#(int) cycle <- mkReg(0);
48 //External memory
49 // I'm not comfortable assuming that the memory subsystem is in order
50 // So I'll insert a completion buffer here.
51 ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR();
52 // Make this big enough so that several outstanding requests may be supported
53 FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
55 // this is for the tracing
56 rule printCycles;
57 cycle <= cycle+1;
58 $fdisplay(stderr, " => Cycle = %d", cycle);
59 endrule
61 rule sendMemReq;
62 let coreReq <- core.mmem_client.request.get;
63 case (coreReq) matches
64 tagged LoadReq .load: begin
65 //Allocate ROB space
66 client_stub.makeRequest_MemoryRequestLoad(load.addr);
67 tags.enq(load.tag);
68 end
69 tagged StoreReq .store: begin
70 client_stub.makeRequest_MemoryRequestStore(store.addr,store.data);
71 end
72 endcase
73 endrule
75 rule receiveMemResp;
76 let memResp <- client_stub.getResponse_MemoryRequestLoad();
77 tags.deq;
78 core.mmem_client.response.put(tagged LoadResp {data:memResp,
79 tag: tags.first});
80 endrule
82 // this isn't particularly correct as it doesn't actually connect the processor interfaces, but this should allow me to verify the data path before fully blending the two items together.
84 rule feedOutput;
85 let pipelineData <- core.sampleOutput.get();
86 AudioProcessorControl endOfFileTag = EndOfFile;
87 AudioProcessorControl sampleTag = Data;
89 // case (pipelineData) matches
90 // tagged EndOfFile:
91 client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?);
92 // tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)), zeroExtend(pack(sample)));
93 // endcase
94 endrule
96 endmodule