import RegFile::*;

 import ProcTypes::*;

 import FIFO::*;

 

 typedef Maybe#(Addr) BrPred;

 typedef Bit#(4) BPindx;

 

 typedef struct {Addr brpc; Addr nextpc;} BrPair deriving (Bits,Eq);

 

 typedef union tagged

 {

   BrPair Valid;

   void Invalid;

 } CBranchPath deriving(Bits, Eq);	// have the cache start out invalid and add valid values.

 

 interface BranchPred;

    method BrPred get(Addr pres);  //returns a maybe type that is invalid if no predition

    method Action upd(Addr pres, Addr next);

 endinterface

 

 module mkBranchPred(BranchPred);

 

    //state variables

    RegFile#(BPindx, CBranchPath)  bcache <- mkRegFileFull(); // cache to hold 16 (based on BPindx)

 

    method Action upd(Addr pres, Addr next);

       BrPair brp;

       brp = BrPair {brpc:pres, nextpc:next};

       bcache.upd(pres[5:2], tagged Valid brp);

    endmethod

 

    method BrPred get(Addr prespc);

       BPindx rd = prespc[5:2];

       let cbp = bcache.sub(rd);

       if (cbp matches tagged Valid .bp &&& bp.brpc == prespc)  //make sure that the read value was actually put there and the full address matches

 	 return tagged Valid bp.nextpc;

       else return Invalid;

    endmethod

    

 endmodule