Mercurial > pygar

     1 // The MIT License

     2 

     3 // Copyright (c) 2009 Massachusetts Institute of Technology

     4 

     5 // Permission is hereby granted, free of charge, to any person obtaining a copy

     6 // of this software and associated documentation files (the "Software"), to deal

     7 // in the Software without restriction, including without limitation the rights

     8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

     9 // copies of the Software, and to permit persons to whom the Software is

    10 // furnished to do so, subject to the following conditions:

    11 

    12 // The above copyright notice and this permission notice shall be included in

    13 // all copies or substantial portions of the Software.

    14 

    15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

    16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

    17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

    18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

    19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

    20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

    21 // THE SOFTWARE.

    22 

    23 // Author: Kermin Fleming kfleming@mit.edu

    24 

    25 import Connectable::*;

    26 import GetPut::*;

    27 import ClientServer::*;

    28 import FIFO::*;

    29 import SpecialFIFOs::*;

    30 

    31 //AWB includes

    32 `include "asim/provides/low_level_platform_interface.bsh"

    33 `include "asim/provides/soft_connections.bsh"

    34 `include "asim/provides/common_services.bsh"

    35 

    36 //Local includes

    37 `include "asim/provides/audio_pipe_types.bsh"  //provides Audio Pipeline interface

    38 `include "asim/provides/path_types.bsh"

    39 `include "asim/provides/core.bsh"

    40 `include "asim/provides/processor_library.bsh"

    41 `include "asim/provides/fpga_components.bsh"

    42 `include "asim/provides/scratchpad_memory.bsh"

    43 `include "asim/provides/mem_services.bsh"

    44 `include "asim/dict/VDEV_SCRATCH.bsh"

    45 

    46 `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"

    47 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"

    48 

    49 module [CONNECTED_MODULE] mkConnectedApplication ();

    50    Core core <- mkCore;

    51    Reg#(int) cycle <- mkReg(0);

    52 

    53   //External memory 

    54   // I'm not comfortable assuming that the memory subsystem is in order  

    55   // So I'll insert a completion buffer here.

    56   MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED);   //Services Memory items

    57 

    58   // Services Samples 

    59   ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR();   

    60   // Make this big enough so that several outstanding requests may be supported

    61   FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);

    62 

    63    //-----------------------------------------------------------

    64    // Debug port

    65    

    66    ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR();   

    67 

    68    

    69   // this is for the tracing

    70   rule printCycles;

    71     cycle <= cycle+1;

    72     $fdisplay(stderr, " => Cycle = %d", cycle);

    73   endrule

    74 

    75   rule sendMemReq;

    76     let coreReq <- core.mmem_client.request.get;

    77     case (coreReq) matches 

    78       tagged LoadReq .load: begin

    79                               //Allocate ROB space

    80                               memory.readReq(truncate(load.addr>>2));

    81                               tags.enq(load.tag);

    82                             end

    83       tagged StoreReq .store: begin

    84 	                      memory.write(truncate(store.addr>>2),store.data);

    85                               end

    86     endcase

    87   endrule

    88   

    89   rule receiveMemResp;

    90     let memResp <- memory.readRsp();

    91     tags.deq;

    92     core.mmem_client.response.put(tagged LoadResp {data:memResp,

    93                                                    tag: tags.first});

    94   endrule

    95 

    96    rule feedOutput;

    97      let pipelineData <- core.sampleOutput.get();

    98      AudioProcessorControl endOfFileTag = EndOfFile;

    99      AudioProcessorControl sampleTag = Data;

   100 

   101      case (pipelineData) matches

   102        tagged EndOfFile: 

   103        client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?);

   104        tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)), zeroExtend(pack(sample)));

   105      endcase

   106    endrule

   107 

   108    //*****  SERVER Side  *****

   109 

   110    (* conservative_implicit_conditions *)

   111   rule handleCPUToHost;

   112    let req <- server_stub.acceptRequest_ReadCPUToHost();

   113     case (req)

   114      0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);

   115     endcase

   116   endrule

   117    

   118    rule feedInput;

   119      let command <- server_stub.acceptRequest_SendUnprocessedStream();

   120      AudioProcessorControl ctrl = unpack(truncate(command.ctrl));

   121      if(ctrl == EndOfFile)

   122 	begin

   123 	  $display("lsp: PROCESSOR received EOF   ");

   124           core.sampleInput.put(tagged EndOfFile);

   125        end

   126      else 

   127 	begin

   128 	  $display("lsp: PROCESSOR received Data   ");

   129           core.sampleInput.put(tagged Sample unpack(truncate(command.sample)));

   130        end

   131    endrule     

   132 endmodule
author	punk
date	Tue, 04 May 2010 19:27:38 -0400
parents	0475235d1513
children	5a30f173bbac