view modules/bluespec/Pygar/core/audioCore.bsv @ 38:05598d745f99 pygar svn.39

[svn r39] fixed audiocorepipe
author punk
date Tue, 04 May 2010 19:27:38 -0400
parents 99519a031813
children a139cc07b773
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1 // The MIT License
3 // Copyright (c) 2009 Massachusetts Institute of Technology
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
23 import Connectable::*;
24 import GetPut::*;
25 import ClientServer::*;
26 import Processor::*;
27 import MemArb::*;
28 import MemTypes::*;
30 //AWB includes
31 `include "asim/provides/low_level_platform_interface.bsh"
32 `include "asim/provides/soft_connections.bsh"
33 `include "asim/provides/common_services.bsh"
35 // Local includes
36 `include "asim/provides/processor_library.bsh"
37 `include "asim/provides/mem_arb.bsh"
38 `include "asim/provides/instruction_cache.bsh"
39 `include "asim/provides/data_cache.bsh"
40 `include "asim/provides/processor.bsh"
41 `include "asim/provides/audio_pipe_types.bsh"
43 interface Core;
45 // Interface from core to main memory
46 interface Client#(MainMemReq,MainMemResp) mmem_client;
48 interface Get#(AudioProcessorUnit) sampleOutput;
49 interface Put#(AudioProcessorUnit) sampleInput;
51 // interface CPUToHost tohost;
53 endinterface
55 module [CONNECTED_MODULE] mkCore( Core );
57 // Instantiate the modules
59 Proc proc <- mkProc();
60 ICache#(InstReq,InstResp) icache <- mkInstCache();
61 DCache#(DataReq,DataResp) dcache <- mkDataCache();
62 MemArb marb <- mkMemArb();
64 // Internal connections
66 mkConnection( proc.statsEn_get, icache.statsEn_put );
67 mkConnection( proc.statsEn_get, dcache.statsEn_put );
68 mkConnection( proc.imem_client, icache.proc_server );
69 mkConnection( proc.dmem_client, dcache.proc_server );
70 mkConnection( icache.mmem_client, marb.cache0_server );
71 mkConnection( dcache.mmem_client, marb.cache1_server );
73 // Methods
75 interface mmem_client = marb.mmem_client;
77 interface sampleOutput = proc.sampleOutput;
78 interface sampleInput = proc.sampleInput;
80 // interface CPUToHost tohost = proc.tohost;
82 endmodule