Mercurial > pygar
diff modules/bluespec/Pygar/core/ProcTrace.bsv~ @ 26:f5dfbe28fa59 pygar svn.27
[svn r27] Fixed Instruction trace issue.
| author | punk |
|---|---|
| date | Fri, 30 Apr 2010 09:03:10 -0400 |
| parents | |
| children |
line wrap: on
line diff
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/modules/bluespec/Pygar/core/ProcTrace.bsv~ Fri Apr 30 09:03:10 2010 -0400 1.3 @@ -0,0 +1,375 @@ 1.4 +import Trace::*; 1.5 + 1.6 + 1.7 +//---------------------------------------------------------------------- 1.8 +// Other typedefs 1.9 +//---------------------------------------------------------------------- 1.10 + 1.11 +typedef Bit#(32) Addr; 1.12 +typedef Int#(18) Stat; 1.13 + 1.14 +//---------------------------------------------------------------------- 1.15 +// Basic instruction type 1.16 +//---------------------------------------------------------------------- 1.17 + 1.18 +typedef Bit#(5) Rindx; 1.19 +typedef Bit#(16) Simm; 1.20 +typedef Bit#(16) Zimm; 1.21 +typedef Bit#(8) Epoch; 1.22 +typedef Bit#(5) Shamt; 1.23 +typedef Bit#(26) Target; 1.24 +typedef Bit#(5) CP0indx; 1.25 +typedef Bit#(32) Data; 1.26 + 1.27 +typedef enum 1.28 +{ 1.29 + Taken, 1.30 + NotTaken 1.31 +} 1.32 + Direction 1.33 + deriving(Bits,Eq); 1.34 + 1.35 + 1.36 +//---------------------------------------------------------------------- 1.37 +// Pipeline typedefs 1.38 +//---------------------------------------------------------------------- 1.39 + 1.40 +typedef union tagged 1.41 +{ 1.42 + Tuple2#(Rindx,Data) ALUWB; 1.43 + Rindx MemWB; 1.44 + Tuple2#(Rindx,Data) CoWB; 1.45 +} 1.46 + WritebackType 1.47 + deriving(Bits,Eq); 1.48 + 1.49 +//////////////////////// 1.50 +// I Add Writeback queue type 1.51 +//////////// 1.52 +typedef union tagged 1.53 +{ 1.54 + struct {Bit#(32) data; Rindx dest; } WB_ALU; 1.55 + Bit#(32) WB_Host; 1.56 + Rindx WB_Load; 1.57 + void WB_Store; 1.58 +} 1.59 +WBResult deriving(Eq, Bits); 1.60 + 1.61 +typedef struct{Addr qpc; Addr qnxtpc; Epoch qepoch;} PCStat deriving(Eq, Bits); 1.62 +//typedef struct{Addr qpc; Epoch qepoch;} PCStat deriving(Eq, Bits); 1.63 + 1.64 +typedef union tagged 1.65 +{ 1.66 + 1.67 + struct { Rindx rbase; Rindx rdst; Simm offset; } LW; 1.68 + struct { Rindx rbase; Rindx rsrc; Simm offset; } SW; 1.69 + 1.70 + struct { Rindx rsrc; Rindx rdst; Simm imm; } ADDIU; 1.71 + struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTI; 1.72 + struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTIU; 1.73 + struct { Rindx rsrc; Rindx rdst; Zimm imm; } ANDI; 1.74 + struct { Rindx rsrc; Rindx rdst; Zimm imm; } ORI; 1.75 + struct { Rindx rsrc; Rindx rdst; Zimm imm; } XORI; 1.76 + struct { Rindx rdst; Zimm imm; } LUI; 1.77 + 1.78 + struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SLL; 1.79 + struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRL; 1.80 + struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRA; 1.81 + struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SLLV; 1.82 + struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRLV; 1.83 + struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRAV; 1.84 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } ADDU; 1.85 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SUBU; 1.86 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } AND; 1.87 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } OR; 1.88 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } XOR; 1.89 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } NOR; 1.90 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLT; 1.91 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLTU; 1.92 + 1.93 + struct { Target target; } J; 1.94 + struct { Target target; } JAL; 1.95 + struct { Rindx rsrc; } JR; 1.96 + struct { Rindx rsrc; Rindx rdst; } JALR; 1.97 + struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BEQ; 1.98 + struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BNE; 1.99 + struct { Rindx rsrc; Simm offset; } BLEZ; 1.100 + struct { Rindx rsrc; Simm offset; } BGTZ; 1.101 + struct { Rindx rsrc; Simm offset; } BLTZ; 1.102 + struct { Rindx rsrc; Simm offset; } BGEZ; 1.103 + 1.104 + struct { Rindx rdst; CP0indx cop0src; } MFC0; 1.105 + struct { Rindx rsrc; CP0indx cop0dst; } MTC0; 1.106 + 1.107 + void ILLEGAL; 1.108 + 1.109 +} 1.110 +Instr deriving(Eq); 1.111 + 1.112 +//---------------------------------------------------------------------- 1.113 +// Pack and Unpack 1.114 +//---------------------------------------------------------------------- 1.115 + 1.116 +Bit#(6) opFUNC = 6'b000000; Bit#(6) fcSLL = 6'b000000; 1.117 +Bit#(6) opRT = 6'b000001; Bit#(6) fcSRL = 6'b000010; 1.118 +Bit#(6) opRS = 6'b010000; Bit#(6) fcSRA = 6'b000011; 1.119 + Bit#(6) fcSLLV = 6'b000100; 1.120 +Bit#(6) opLW = 6'b100011; Bit#(6) fcSRLV = 6'b000110; 1.121 +Bit#(6) opSW = 6'b101011; Bit#(6) fcSRAV = 6'b000111; 1.122 + Bit#(6) fcADDU = 6'b100001; 1.123 +Bit#(6) opADDIU = 6'b001001; Bit#(6) fcSUBU = 6'b100011; 1.124 +Bit#(6) opSLTI = 6'b001010; Bit#(6) fcAND = 6'b100100; 1.125 +Bit#(6) opSLTIU = 6'b001011; Bit#(6) fcOR = 6'b100101; 1.126 +Bit#(6) opANDI = 6'b001100; Bit#(6) fcXOR = 6'b100110; 1.127 +Bit#(6) opORI = 6'b001101; Bit#(6) fcNOR = 6'b100111; 1.128 +Bit#(6) opXORI = 6'b001110; Bit#(6) fcSLT = 6'b101010; 1.129 +Bit#(6) opLUI = 6'b001111; Bit#(6) fcSLTU = 6'b101011; 1.130 + 1.131 +Bit#(6) opJ = 6'b000010; 1.132 +Bit#(6) opJAL = 6'b000011; 1.133 +Bit#(6) fcJR = 6'b001000; 1.134 +Bit#(6) fcJALR = 6'b001001; 1.135 +Bit#(6) opBEQ = 6'b000100; 1.136 +Bit#(6) opBNE = 6'b000101; 1.137 +Bit#(6) opBLEZ = 6'b000110; 1.138 +Bit#(6) opBGTZ = 6'b000111; 1.139 +Bit#(5) rtBLTZ = 5'b00000; 1.140 +Bit#(5) rtBGEZ = 5'b00001; 1.141 + 1.142 +Bit#(5) rsMFC0 = 5'b00000; 1.143 +Bit#(5) rsMTC0 = 5'b00100; 1.144 + 1.145 +instance Bits#(Instr,32); 1.146 + 1.147 + // Pack Function 1.148 + 1.149 + function Bit#(32) pack( Instr instr ); 1.150 + 1.151 + case ( instr ) matches 1.152 + 1.153 + tagged LW .it : return { opLW, it.rbase, it.rdst, it.offset }; 1.154 + tagged SW .it : return { opSW, it.rbase, it.rsrc, it.offset }; 1.155 + 1.156 + tagged ADDIU .it : return { opADDIU, it.rsrc, it.rdst, it.imm }; 1.157 + tagged SLTI .it : return { opSLTI, it.rsrc, it.rdst, it.imm }; 1.158 + tagged SLTIU .it : return { opSLTIU, it.rsrc, it.rdst, it.imm }; 1.159 + tagged ANDI .it : return { opANDI, it.rsrc, it.rdst, it.imm }; 1.160 + tagged ORI .it : return { opORI, it.rsrc, it.rdst, it.imm }; 1.161 + tagged XORI .it : return { opXORI, it.rsrc, it.rdst, it.imm }; 1.162 + tagged LUI .it : return { opLUI, 5'b0, it.rdst, it.imm }; 1.163 + 1.164 + tagged SLL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSLL }; 1.165 + tagged SRL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRL }; 1.166 + tagged SRA .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRA }; 1.167 + 1.168 + tagged SLLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSLLV }; 1.169 + tagged SRLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRLV }; 1.170 + tagged SRAV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRAV }; 1.171 + 1.172 + tagged ADDU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcADDU }; 1.173 + tagged SUBU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSUBU }; 1.174 + tagged AND .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcAND }; 1.175 + tagged OR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcOR }; 1.176 + tagged XOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcXOR }; 1.177 + tagged NOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcNOR }; 1.178 + tagged SLT .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLT }; 1.179 + tagged SLTU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLTU }; 1.180 + 1.181 + tagged J .it : return { opJ, it.target }; 1.182 + tagged JAL .it : return { opJAL, it.target }; 1.183 + tagged JR .it : return { opFUNC, it.rsrc, 5'b0, 5'b0, 5'b0, fcJR }; 1.184 + tagged JALR .it : return { opFUNC, it.rsrc, 5'b0, it.rdst, 5'b0, fcJALR }; 1.185 + tagged BEQ .it : return { opBEQ, it.rsrc1, it.rsrc2, it.offset }; 1.186 + tagged BNE .it : return { opBNE, it.rsrc1, it.rsrc2, it.offset }; 1.187 + tagged BLEZ .it : return { opBLEZ, it.rsrc, 5'b0, it.offset }; 1.188 + tagged BGTZ .it : return { opBGTZ, it.rsrc, 5'b0, it.offset }; 1.189 + tagged BLTZ .it : return { opRT, it.rsrc, rtBLTZ, it.offset }; 1.190 + tagged BGEZ .it : return { opRT, it.rsrc, rtBGEZ, it.offset }; 1.191 + 1.192 + tagged MFC0 .it : return { opRS, rsMFC0, it.rdst, it.cop0src, 11'b0 }; 1.193 + tagged MTC0 .it : return { opRS, rsMTC0, it.rsrc, it.cop0dst, 11'b0 }; 1.194 + 1.195 + endcase 1.196 + 1.197 + endfunction 1.198 + 1.199 + // Unpack Function 1.200 + 1.201 + function Instr unpack( Bit#(32) instrBits ); 1.202 + 1.203 + let opcode = instrBits[ 31 : 26 ]; 1.204 + let rs = instrBits[ 25 : 21 ]; 1.205 + let rt = instrBits[ 20 : 16 ]; 1.206 + let rd = instrBits[ 15 : 11 ]; 1.207 + let shamt = instrBits[ 10 : 6 ]; 1.208 + let funct = instrBits[ 5 : 0 ]; 1.209 + let imm = instrBits[ 15 : 0 ]; 1.210 + let target = instrBits[ 25 : 0 ]; 1.211 + 1.212 + case ( opcode ) 1.213 + 1.214 + opLW : return LW { rbase:rs, rdst:rt, offset:imm }; 1.215 + opSW : return SW { rbase:rs, rsrc:rt, offset:imm }; 1.216 + opADDIU : return ADDIU { rsrc:rs, rdst:rt, imm:imm }; 1.217 + opSLTI : return SLTI { rsrc:rs, rdst:rt, imm:imm }; 1.218 + opSLTIU : return SLTIU { rsrc:rs, rdst:rt, imm:imm }; 1.219 + opANDI : return ANDI { rsrc:rs, rdst:rt, imm:imm }; 1.220 + opORI : return ORI { rsrc:rs, rdst:rt, imm:imm }; 1.221 + opXORI : return XORI { rsrc:rs, rdst:rt, imm:imm }; 1.222 + opLUI : return LUI { rdst:rt, imm:imm }; 1.223 + opJ : return J { target:target }; 1.224 + opJAL : return JAL { target:target }; 1.225 + opBEQ : return BEQ { rsrc1:rs, rsrc2:rt, offset:imm }; 1.226 + opBNE : return BNE { rsrc1:rs, rsrc2:rt, offset:imm }; 1.227 + opBLEZ : return BLEZ { rsrc:rs, offset:imm }; 1.228 + opBGTZ : return BGTZ { rsrc:rs, offset:imm }; 1.229 + 1.230 + opFUNC : 1.231 + case ( funct ) 1.232 + fcSLL : return SLL { rsrc:rt, rdst:rd, shamt:shamt }; 1.233 + fcSRL : return SRL { rsrc:rt, rdst:rd, shamt:shamt }; 1.234 + fcSRA : return SRA { rsrc:rt, rdst:rd, shamt:shamt }; 1.235 + fcSLLV : return SLLV { rsrc:rt, rdst:rd, rshamt:rs }; 1.236 + fcSRLV : return SRLV { rsrc:rt, rdst:rd, rshamt:rs }; 1.237 + fcSRAV : return SRAV { rsrc:rt, rdst:rd, rshamt:rs }; 1.238 + fcADDU : return ADDU { rsrc1:rs, rsrc2:rt, rdst:rd }; 1.239 + fcSUBU : return SUBU { rsrc1:rs, rsrc2:rt, rdst:rd }; 1.240 + fcAND : return AND { rsrc1:rs, rsrc2:rt, rdst:rd }; 1.241 + fcOR : return OR { rsrc1:rs, rsrc2:rt, rdst:rd }; 1.242 + fcXOR : return XOR { rsrc1:rs, rsrc2:rt, rdst:rd }; 1.243 + fcNOR : return NOR { rsrc1:rs, rsrc2:rt, rdst:rd }; 1.244 + fcSLT : return SLT { rsrc1:rs, rsrc2:rt, rdst:rd }; 1.245 + fcSLTU : return SLTU { rsrc1:rs, rsrc2:rt, rdst:rd }; 1.246 + fcJR : return JR { rsrc:rs }; 1.247 + fcJALR : return JALR { rsrc:rs, rdst:rd }; 1.248 + default : return ILLEGAL; 1.249 + endcase 1.250 + 1.251 + opRT : 1.252 + case ( rt ) 1.253 + rtBLTZ : return BLTZ { rsrc:rs, offset:imm }; 1.254 + rtBGEZ : return BGEZ { rsrc:rs, offset:imm }; 1.255 + default : return ILLEGAL; 1.256 + endcase 1.257 + 1.258 + opRS : 1.259 + case ( rs ) 1.260 + rsMFC0 : return MFC0 { rdst:rt, cop0src:rd }; 1.261 + rsMTC0 : return MTC0 { rsrc:rt, cop0dst:rd }; 1.262 + default : return ILLEGAL; 1.263 + endcase 1.264 + 1.265 + default : return ILLEGAL; 1.266 + 1.267 + endcase 1.268 + 1.269 + endfunction 1.270 + 1.271 +endinstance 1.272 + 1.273 +//---------------------------------------------------------------------- 1.274 +// Trace 1.275 +//---------------------------------------------------------------------- 1.276 + 1.277 +instance Traceable#(Instr); 1.278 + 1.279 + function Action traceTiny( String loc, String ttag, Instr inst ); 1.280 + case ( inst ) matches 1.281 + 1.282 + tagged LW .it : $fdisplay(stderr, " => %s:%s lw", loc, ttag ); 1.283 + tagged SW .it : $fdisplay(stderr, " => %s:%s sw", loc, ttag ); 1.284 + 1.285 + tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addi", loc, ttag ); 1.286 + tagged SLTI .it : $fdisplay(stderr, " => %s:%s sli", loc, ttag ); 1.287 + tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sliu", loc, ttag ); 1.288 + tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi", loc, ttag ); 1.289 + tagged ORI .it : $fdisplay(stderr, " => %s:%s ori", loc, ttag ); 1.290 + tagged XORI .it : $fdisplay(stderr, " => %s:%s xori", loc, ttag ); 1.291 + tagged LUI .it : $fdisplay(stderr, " => %s:%s lui", loc, ttag ); 1.292 + 1.293 + tagged SLL .it : $fdisplay(stderr, " => %s:%s sll", loc, ttag ); 1.294 + tagged SRL .it : $fdisplay(stderr, " => %s:%s srl", loc, ttag ); 1.295 + tagged SRA .it : $fdisplay(stderr, " => %s:%s sra", loc, ttag ); 1.296 + tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv", loc, ttag ); 1.297 + tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv", loc, ttag ); 1.298 + tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav", loc, ttag ); 1.299 + 1.300 + tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu", loc, ttag ); 1.301 + tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu", loc, ttag ); 1.302 + tagged AND .it : $fdisplay(stderr, " => %s:%s and", loc, ttag ); 1.303 + tagged OR .it : $fdisplay(stderr, " => %s:%s or", loc, ttag ); 1.304 + tagged XOR .it : $fdisplay(stderr, " => %s:%s xor", loc, ttag ); 1.305 + tagged NOR .it : $fdisplay(stderr, " => %s:%s nor", loc, ttag ); 1.306 + tagged SLT .it : $fdisplay(stderr, " => %s:%s slt", loc, ttag ); 1.307 + tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu", loc, ttag ); 1.308 + 1.309 + tagged J .it : $fdisplay(stderr, " => %s:%s j", loc, ttag ); 1.310 + tagged JAL .it : $fdisplay(stderr, " => %s:%s jal", loc, ttag ); 1.311 + tagged JR .it : $fdisplay(stderr, " => %s:%s jr", loc, ttag ); 1.312 + tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr", loc, ttag ); 1.313 + tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq", loc, ttag ); 1.314 + tagged BNE .it : $fdisplay(stderr, " => %s:%s bne", loc, ttag ); 1.315 + tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez", loc, ttag ); 1.316 + tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz", loc, ttag ); 1.317 + tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz", loc, ttag ); 1.318 + tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez", loc, ttag ); 1.319 + 1.320 + tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0", loc, ttag ); 1.321 + tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0", loc, ttag ); 1.322 + 1.323 + tagged ILLEGAL : $fdisplay(stderr, " => %s:%s ill", loc, ttag ); 1.324 + 1.325 + endcase 1.326 + endfunction 1.327 + 1.328 + function Action traceFull( String loc, String ttag, Instr inst ); 1.329 + case ( inst ) matches 1.330 + 1.331 + tagged LW .it : $fdisplay(stderr, " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase ); 1.332 + tagged SW .it : $fdisplay(stderr, " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase ); 1.333 + 1.334 + tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 1.335 + tagged SLTI .it : $fdisplay(stderr, " => %s:%s slti r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 1.336 + tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 1.337 + tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 1.338 + tagged ORI .it : $fdisplay(stderr, " => %s:%s ori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 1.339 + tagged XORI .it : $fdisplay(stderr, " => %s:%s xori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 1.340 + tagged LUI .it : $fdisplay(stderr, " => %s:%s lui r%0d, 0x%x", loc, ttag, it.rdst, it.imm ); 1.341 + 1.342 + tagged SLL .it : $fdisplay(stderr, " => %s:%s sll r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); 1.343 + tagged SRL .it : $fdisplay(stderr, " => %s:%s srl r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); 1.344 + tagged SRA .it : $fdisplay(stderr, " => %s:%s sra r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); 1.345 + tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); 1.346 + tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); 1.347 + tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); 1.348 + 1.349 + tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 1.350 + tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 1.351 + tagged AND .it : $fdisplay(stderr, " => %s:%s and r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 1.352 + tagged OR .it : $fdisplay(stderr, " => %s:%s or r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 1.353 + tagged XOR .it : $fdisplay(stderr, " => %s:%s xor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 1.354 + tagged NOR .it : $fdisplay(stderr, " => %s:%s nor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 1.355 + tagged SLT .it : $fdisplay(stderr, " => %s:%s slt r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 1.356 + tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 1.357 + 1.358 + tagged J .it : $fdisplay(stderr, " => %s:%s j 0x%x", loc, ttag, it.target ); 1.359 + tagged JAL .it : $fdisplay(stderr, " => %s:%s jal 0x%x", loc, ttag, it.target ); 1.360 + tagged JR .it : $fdisplay(stderr, " => %s:%s jr r%0d", loc, ttag, it.rsrc ); 1.361 + tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr r%0d", loc, ttag, it.rsrc ); 1.362 + tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); 1.363 + tagged BNE .it : $fdisplay(stderr, " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); 1.364 + tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 1.365 + tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 1.366 + tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 1.367 + tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 1.368 + 1.369 + tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src ); 1.370 + tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst ); 1.371 + 1.372 + tagged ILLEGAL : $fdisplay(stderr, " => %s:%s illegal instruction", loc, ttag ); 1.373 + 1.374 + endcase 1.375 + endfunction 1.376 + 1.377 +endinstance 1.378 +