Mercurial > pygar
diff scripts/proc-trace.cfg @ 23:90197e3375e2 pygar svn.24
[svn r24] added testing, but something is wrong with our c++ file.
author | rlm |
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date | Wed, 28 Apr 2010 08:19:09 -0400 |
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1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/scripts/proc-trace.cfg Wed Apr 28 08:19:09 2010 -0400 1.3 @@ -0,0 +1,99 @@ 1.4 +#========================================================================= 1.5 +# Trace-bsv.pl Config File 1.6 +# 1.7 + 1.8 +package settings; 1.9 + 1.10 +#-------------------------------------------------------------------- 1.11 +# Trace Tags 1.12 +#-------------------------------------------------------------------- 1.13 + 1.14 +$base = "mkCoreTH_wrapper.coreTH"; 1.15 + 1.16 +# This should be a hash of tags to what should be displayed if the 1.17 +# tag is not present on a given cycle. The tags correspond to the 1.18 +# trace tags used in the BSV source code. 1.19 + 1.20 +%fields = 1.21 +( 1.22 + 1.23 + "mkProc:pc" => " ", 1.24 + "mkProc:pcgen" => " ", 1.25 + "mkProc:exec" => " ", 1.26 + "mkProc:writeback" => " ", 1.27 + "mkProc:exInstFull" => " ", 1.28 + 1.29 + "mkInstCacheBlocking:reqTiny" => " ", 1.30 + "mkInstCacheBlocking:respTiny" => " ", 1.31 + "mkInstCacheBlocking:stage" => " ", 1.32 + "mkInstCacheBlocking:hitMiss" => " ", 1.33 + 1.34 + "mkDataCacheBlocking:reqTiny" => " ", 1.35 + "mkDataCacheBlocking:respTiny" => " ", 1.36 + "mkDataCacheBlocking:stage" => " ", 1.37 + "mkDataCacheBlocking:hitMiss" => " ", 1.38 + 1.39 + "mkMemArb:req0" => " ", 1.40 + "mkMemArb:req1" => " ", 1.41 + "mkMemArb:resp" => " ", 1.42 + 1.43 +); 1.44 + 1.45 +%headers = 1.46 +( 1.47 + 1.48 + "mkProc:pc" => "pc ", 1.49 + "mkProc:pcgen" => "stage", 1.50 + "mkProc:exec" => "", 1.51 + "mkProc:writeback" => "", 1.52 + "mkProc:exInstFull" => "exInst ", 1.53 + 1.54 + "mkInstCacheBlocking:reqTiny" => "req", 1.55 + "mkInstCacheBlocking:respTiny" => "resp", 1.56 + "mkInstCacheBlocking:stage" => "stage", 1.57 + "mkInstCacheBlocking:hitMiss" => "hit/miss", 1.58 + 1.59 + "mkDataCacheBlocking:reqTiny" => "req", 1.60 + "mkDataCacheBlocking:respTiny" => "resp", 1.61 + "mkDataCacheBlocking:stage" => "stage", 1.62 + "mkDataCacheBlocking:hitMiss" => "hit/miss", 1.63 + 1.64 + "mkMemArb:req0" => "req0", 1.65 + "mkMemArb:req1" => "req1", 1.66 + "mkMemArb:resp" => "req2", 1.67 + 1.68 +); 1.69 + 1.70 + 1.71 +#-------------------------------------------------------------------- 1.72 +# Trace String 1.73 +#-------------------------------------------------------------------- 1.74 + 1.75 +# For the processor we display the PC and what stage we are in. 1.76 + 1.77 +$proc = "pc={mkProc:pc} [{mkProc:pcgen}|{mkProc:exec}|{mkProc:writeback}]"; 1.78 +$procl = "{mkProc:pc} [{mkProc:pcgen}{mkProc:exec}{mkProc:writeback}]"; 1.79 + 1.80 +# For the caches we display the current request and response, 1.81 +# the current cache stage, whether or not the access is a hit or a miss. 1.82 + 1.83 +$icache = "[{mkInstCacheBlocking:reqTiny}|{mkInstCacheBlocking:respTiny}|". 1.84 + "{mkInstCacheBlocking:stage}|{mkInstCacheBlocking:hitMiss}]"; 1.85 + 1.86 +$dcache = "[{mkDataCacheBlocking:reqTiny}|{mkDataCacheBlocking:respTiny}|". 1.87 + "{mkDataCacheBlocking:stage}|{mkDataCacheBlocking:hitMiss}]"; 1.88 + 1.89 +# For the memory arbiter we display the two requests from the 1.90 +# instruction and data caches and the response (which might be 1.91 +# going to either cache) 1.92 + 1.93 +$marb = "[{mkMemArb:req0}|{mkMemArb:req1}|{mkMemArb:resp}]"; 1.94 + 1.95 +# The trace string is used by bsv-trace.pl to for one line trace 1.96 +# output. Basically the current value for a given tag is substituted 1.97 +# into the trace string every cycle. If the tag is not present then 1.98 +# the empty field is used form the %fields hash. 1.99 + 1.100 +$traceString = "$proc $icache $dcache $marb {mkProc:exInstFull} "; 1.101 +$labelString = "$procl $icache $dcache $marb {mkProc:exInstFull} "; 1.102 +