diff modules/bluespec/Pygar/lab4/ProcessorSystem.bsv @ 8:74716e9a81cc pygar svn.9

[svn r9] Pygar now has the proper directory structure to play nicely with awb. Also, the apm file for audio-core willcompile successfully.
author rlm
date Fri, 23 Apr 2010 02:32:05 -0400
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     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/modules/bluespec/Pygar/lab4/ProcessorSystem.bsv	Fri Apr 23 02:32:05 2010 -0400
     1.3 @@ -0,0 +1,82 @@
     1.4 +// The MIT License
     1.5 +
     1.6 +// Copyright (c) 2009 Massachusetts Institute of Technology
     1.7 +
     1.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy
     1.9 +// of this software and associated documentation files (the "Software"), to deal
    1.10 +// in the Software without restriction, including without limitation the rights
    1.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    1.12 +// copies of the Software, and to permit persons to whom the Software is
    1.13 +// furnished to do so, subject to the following conditions:
    1.14 +
    1.15 +// The above copyright notice and this permission notice shall be included in
    1.16 +// all copies or substantial portions of the Software.
    1.17 +
    1.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    1.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
    1.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    1.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    1.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    1.24 +// THE SOFTWARE.
    1.25 +
    1.26 +import Connectable::*;
    1.27 +import GetPut::*;
    1.28 +import ClientServer::*;
    1.29 +import FIFO::*;
    1.30 +import SpecialFIFOs::*;
    1.31 +
    1.32 +//AWB includes
    1.33 +`include "asim/provides/low_level_platform_interface.bsh"
    1.34 +`include "asim/provides/soft_connections.bsh"
    1.35 +`include "asim/provides/common_services.bsh"
    1.36 +
    1.37 +
    1.38 +// Local includes
    1.39 +`include "asim/provides/core.bsh"
    1.40 +`include "asim/provides/processor_library.bsh"
    1.41 +`include "asim/provides/processor_library.bsh"
    1.42 +`include "asim/provides/fpga_components.bsh"
    1.43 +`include "asim/rrr/remote_client_stub_PROCESSORSYSTEMRRR.bsh"
    1.44 +
    1.45 +module [CONNECTED_MODULE] mkConnectedApplication ();
    1.46 +
    1.47 +  Core core <- mkCore;
    1.48 +  Reg#(int) cycle <- mkReg(0);
    1.49 +
    1.50 +  //External memory 
    1.51 +  // I'm not comfortable assuming that the memory subsystem is in order  
    1.52 +  // So I'll insert a completion buffer here.  
    1.53 +  ClientStub_PROCESSORSYSTEMRRR client_stub <- mkClientStub_PROCESSORSYSTEMRRR();   
    1.54 +  // Make this big enough so that several outstanding requests may be supported
    1.55 +  FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
    1.56 +
    1.57 +  // this is for the tracing
    1.58 +  rule printCycles;
    1.59 +    cycle <= cycle+1;
    1.60 +    $fdisplay(stderr, " => Cycle = %d", cycle);
    1.61 +  endrule
    1.62 +
    1.63 +
    1.64 +  rule sendMemReq;
    1.65 +    let coreReq <- core.mmem_client.request.get;
    1.66 +    case (coreReq) matches 
    1.67 +      tagged LoadReq .load: begin
    1.68 +                              //Allocate ROB space
    1.69 +                              client_stub.makeRequest_MemoryRequestLoad(load.addr);
    1.70 +                              tags.enq(load.tag);
    1.71 +                            end
    1.72 +      tagged StoreReq .store: begin
    1.73 +                                client_stub.makeRequest_MemoryRequestStore(store.addr,store.data);
    1.74 +                              end
    1.75 +    endcase
    1.76 +  endrule
    1.77 +  
    1.78 +  rule receiveMemResp;
    1.79 +    let memResp <- client_stub.getResponse_MemoryRequestLoad();
    1.80 +    tags.deq;
    1.81 +    core.mmem_client.response.put(tagged LoadResp {data:memResp,
    1.82 +                                                   tag: tags.first});
    1.83 +  endrule
    1.84 +
    1.85 +endmodule
    1.86 \ No newline at end of file